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Mutation-Based Test Generation for PLC Embedded Software Using Model Checking 28th

Mutation-Based Test Generation for PLC Embedded Software Usi...

引用

28th IFIP WG 6.1 international conference on Testing Software and Systems (ICTSS)

作者： Enoiu, Eduard P. Sundmark, Daniel Causevic, Adnan Feldt, Robert Pettersson, Paul Malardalen Univ Software Testing Lab Vasteras Sweden Blekinge Inst Technol Karlskrona Sweden

ISBN: (纸本)9783319474434;9783319474427

Testing is an important activity in engineering of industrial embedded software. In certain application domains (e.g., railway industry) engineering software is certified according to safety standards that require extensive software testing procedures to be applied for the development of reliable systems. Mutation analysis is a technique for creating faulty versions of a software for the purpose of examining the fault detection ability of a test suite. Mutation analysis has been used for evaluating existing test suites, but also for generating test suites that detect injected faults (i.e., mutation testing). To support developers in software testing, we propose a technique for producing test cases using an automated test generation approach that operates using mutation testing for software written in IEC 61131-3 language, a programming standard for safety-critical embedded software, commonly used for Programmable logic Controllers (PLCs). this approach uses the Uppaal model checker and is based on a combined model that contains all the mutants and the original program. We applied this approach in a tool for testing industrial PLC programs and evaluated it in terms of cost and fault detection. For realistic validation we collected industrial experimental evidence on how mutation testing compares with manual testing as well as automated decision-coverage adequate test generation. In the evaluation, we used manually seeded faults provided by four industrial engineers. the results show that even if mutation-based test generation achieves better fault detection than automated decision coverage-based test generation, these mutation-adequate test suites are not better at detecting faults than manual test suites. However, the mutation-based test suites are significantly less costly to create, in terms of testing time, than manually created test suites. Our results suggest that the fault detection scores could be improved by considering some new and improved mutation operato

关键词： Programmable logic controllers

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LLM-based methods for the creation of unit tests in game development 28th

LLM-based methods for the creation of unit tests in game dev...

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28th international conference on Knowledge Based and Intelligent information and Engineering Systems, KES 2024

作者： Paduraru, Ciprian Staicu, Adelina Stefanescu, Alin University of Bucharest Department of Computer Science Romania Institute of Logic and Data Science Romania

Problems related to the quality of games, whether on the initial release or after updates, can lead to player dissatisfaction, media attention, and potential financial setbacks. these issues can stem from software bugs, performance bottlenecks, or security vulnerabilities. Despite these challenges, game developers often rely on manual playtesting, highlighting the need for more robust and automated processes in game development. this research explores the application of Large Language Models (LLMs) to automate the creation of unit tests in game development, focusing on strongly typed programming languages such as C++ and C#, which are widely used in the industry. the study focuses on fine-tuning Code Llama, an advanced code generation model, to address common scenarios in game development, including game engines and specific APIs or backends. Although the prototyping and evaluations primarily took place within the Unity game engine, the proposed methods can be adapted to other internal or publicly available solutions. the evaluation results demonstrate these methods' effectiveness in improving existing unit test suites or automatically generating new tests based on natural language descriptions of class contexts and targeted methods. © 2024 the Authors.

关键词： C++ (programming language)

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Characterization of a new L-shaped MOSFET for future deca nano application

Characterization of a new L-shaped MOSFET for future deca na...

引用

international conference on Microelectronics, MIEL

作者： Po-Hsieh Lin Jyi-Tsong Lin Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung Taiwan

A novel device architecture called L-shaped MOSFET has been designed and fabricated. Bulk silicon wafer is used and less area is derived for the device at the same gate length when compared to the conventional MOSFET, thus the fabrication cost is significantly reduced for the future 3D IC applications. Based on the measurement, the new L-shaped MOSFET demonstrates the conventional DC properties properly and possesses different electrical performance when switching its source and drain biases. Simulation results were also performed to prove its novel characteristics when compared to the conventional MOSFET device.

关键词： logic gates MOSFET circuits Performance evaluation Electric fields Fabrication Simulation conferences

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Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic programming

Design of a Compact Reversible Carry Look-Ahead Adder Using ...

引用

international conference on VLSI Design

作者： Nusrat Jahan Lisa Hafiz Md. Hasan Babu Department of Computer Science and Engineering Ahasnaullah University of Science and Technology Dhaka Bangladesh Dhaka University Dhaka Dhaka District BD

this paper presents a new method for designing a reversible carry look-ahead adder (RCLA) based on dynamic programming. In this method, we propose a faster technique for generating carry output, which also outperforms the existing ones in terms of number of operations. In addition, we design a compact reversible carry look-ahead circuit based on the proposed technique. In order to optimize our design, we propose a first ever known Reversible Partial Adder (RPA) circuit with the optimum numbers of the quantum cost and garbage outputs which concurrently produce carry propagation signal, carry generation signal and summation of the inputs. Using RPA as a unit element of RCLA construction, we optimize the designs of RCLA and show that the proposed design is better than the existing ones in terms of the number of gates, quantum cost, garbage outputs and delay with the help of Micro wind DSCH 3.5, e.g., the proposed 128-bit adder improves 77.55% on number of gates, 10% on garbage outputs, 2.16% on delay and 77.61% on quantum cost over the existing best one.

关键词： Adders logic gates Delays Complexity theory Hardware Dynamic programming Algorithm design and analysis

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NeoSilicon based nanoelectromechanical information devices

NeoSilicon based nanoelectromechanical information devices

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international conference on Microelectronics, MIEL

作者： Shunri Oda Quantum Nanoelectronics Research Center Tokyo Institute of Technology Tokyo Japan

NeoSilicon is a novel functional material consisted of ensemble of nanocrystalline Si quantum dots with controlled dot size and inter-dot distance. Bandgap of NeoSilicon can be controlled by dot size due to the quantum size effect and transport properties are controlled by inter-dot distance due to the tunneling effect. A variety of new applications, such as ballistic electron surface emitting display, high-efficiency light-emitting devices and photovoltaic devices is expected. MOS and NEM hybrid devices are promising for logic, memory and sensing applications, since new functions with ultralow power consumption are expected. Further scaling of NEM devices may provide novel functions based on unique phonon dispersion characteristics in nm-scale. Precise control of charge states in the multiple-coupled quantum dots is essential for spin based quantum information processing. In this talk, I will introduce fabrication of highly integrated nanocrystalline Si dots with uniform size, non-volatile NEM memory devices with a bistable floating gate, NEM-SET hybrid transistors, and unique transport processes in multiple-coupled quantum dot systems.

关键词： Silicon Quantum dots Nonvolatile memory logic gates Plasmas Nanoscale devices Tunneling

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Linear processor array in DSP

Linear processor array in DSP

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international conference on Microelectronics, MIEL

作者： I. Ž. Milovanović M. K. Stojčev E. I. Milovanović T. R. Nikolić Faculty of Electronics Engineering Nis Serbia

this article presents the design, implementation and performance evaluation of a hardware accelerator for matrix multiplication. the accelerator is loosely coupled with the host computer via common system bus. the accelerator is composed of linear processor array (LPA), distributed memory and dedicated address generator unit. Mathematical procedure for LPA synthesis is given. the speedup of the proposed accelerator for matrix multiplication is O(n/2), where n is a number of PEs in the array, and the efficiency is 1/2. By involving hardware AGU we achieved a speedup in data transfer of approximately 2.5, compared to the software implementation of address calculation, with a hardware overhead less than 1 %.

关键词： Arrays Hardware Multicore processing logic gates Transmission line matrix methods Delay

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Analytical unified drain current model of long-channel tri-gate FinFETs

Analytical unified drain current model of long-channel tri-g...

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international conference on Microelectronics, MIEL

作者： A. Tsormpatzoglou N. Fasarakis D. H. Tassis I. Pappas K. Papathanasiou C. A. Dimitriadis Department of Physics Aristotle University of Thessaloniki Thessaloniki Greece

A simple unified analytical compact drain current model for undoped (or lightly doped) triple-gate FinFETs is presented, functional for all regions of operation. A unified normalized sheet charge density is used where the behavior of the subthreshold region is embedded within the expressions commonly used to describe the inversion region. the model can be used as a basis for the development of a short-channel model where short-channel effects can be introduced through proper corrections in the core model. the model has been validated by comparing the transfer and output characteristics and their first derivatives with device simulations.

关键词： FinFETs Mathematical model threshold voltage logic gates Analytical models Equations Silicon

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Towards a DGSS Prototype for Early Warning for Ski Injuries

Towards a DGSS Prototype for Early Warning for Ski Injuries

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international conference on Data Engineering Workshops

作者： Boris Delibaic Zoran Obradovic Center for Business Decision-Making University of Belgrade Belgrade Serbia Center for Data Analytics and Biomedical Informatics Temple University Philadelphia PA USA

this paper reports on our ongoing research in ski injury analysis. We propose a decision guidance support system for early warning for ski injuries. We report several injury patterns in form of IF-thEN rules which could be used to build a decision guidance support system for early warning for ski injuries. the rules are induced from data merged from two databases, namely the Mountaineer rescue service database and the Ski gate entrances database. Around 2000 injuries from year 2006 to year 2011 were analyzed. Based on movement of skiers (recorded through ski gates on each lift) several statistics for each accident (e.g. average speed of skier, average weight of slopes) have been calculated.

关键词： Injuries Databases Accidents Snow logic gates Medical diagnostic imaging

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Simulation of current collapse in the 0.25 µm gate Length Al0.28Ga0.72N/GaN HEMT

Simulation of current collapse in the 0.25 µm gate Length A...

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international conference on Microelectronics, MIEL

作者： S. Faramehr K. Kalna P. Igić Electronics Systems Design Centre College of Engineering Swansea University Swansea UK

A 2D drift-diffusion (DD) and Hydrodynamic (HD) transport models within ATLAS simulation toolbox by Silvaco have been calibrated against experimental I-V characteristics of the 0.25μm gate length GaN High Electron Mobility Transistor (HEMT). the simulations take into account both piezoelectric and spontaneous polarization effects at the interface of AlGaN and GaN. the simulations have been employed to investigate the current collapse phenomenon that plays a key role in the output characteristics of a device which can significantly limit the output power. the current collapse is investigated using shallow acceptor traps in the both AlGaN and GaN layers.

关键词： Gallium nitride Electron traps HEMTs Aluminum gallium nitride High definition video logic gates

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Short-circuit ruggedness of high-voltage IGBTs

Short-circuit ruggedness of high-voltage IGBTs

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international conference on Microelectronics, MIEL

作者： J. Lutz T. Basler Power electronics and EMC Department of Electrical Engineering and Information Technology Chemnitz University of Technology Chemnitz Germany Power electronics and EMC Chemnitz University of Technology Germany

the IGBT can run into different short-circuit types (SC I, SC II, SC III). Especially in SC II and III, an interaction between the gate drive unit and the IGBT takes place. A self-turn-off mechanism after short-circuit turn on can occur. Parasitic elements in the connection between the IGBT and the gate unit as well as asymmetrical wiring of devices connected in parallel are of effect to the short-circuit capability. In high-voltage IGBTs, filament formation can occur at short-circuit condition. Destructive measurements with its failure patterns and short-circuit protection methods are shown.

关键词： Insulated gate bipolar transistors logic gates Current measurement Semiconductor device measurement Resistors Capacitance Voltage measurement

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