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检索条件"任意字段=2nd AIZU International Symposium on Parallel Algorithms/Architecture Synthesis"

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parallel algorithm for k-minimum spanning trees

Parallel algorithm for k-minimum spanning trees

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Ma, Jun Iwama, Kazuo Gu, Qian-Ping Shandong Univ Jinan Jinan China

A parallel algorithm to find k, 2 &le k &le nn-2, spanning trees from a connected, weighted and undirected graph G(V, E, W) in the order of increasing weight is presented. It runs in O(T(n) + k log n) time with O(n2/log n) processors on a CREW PRAM, where n = /V/, m = /E/ and T(n), O(log n) &le T(n) &le O(log2 n), is the time of the fastest parallel algorithms to find a minimum spanning tree of G on a CREW PRAM with no more than O(n2/log n) processors. Since T(n) = O(log2 n) for the time being, this result shows that to find k minimum spanning trees can be done in the same time bound as to find just one when k &le O(log n) on a CREW PRAM.

关键词： parallel algorithms

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Efficient processor allocation algorithm using two-dimensional packing

Efficient processor allocation algorithm using two-dimension...

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Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Hwang, Injae Chungbuk Natl Univ Chungbuk Korea Republic of

Mesh is one of the most widely used interconnection networks for multiprocessor systems. In this paper, we propose an approach to partition a given mesh into m submeshes which can be allocated to m tasks with grid structures. We adapt two-dimensional packing to solve the submesh allocation problem. Due to the intractability of the two-dimensional packing problem, finding an optimal solution is computationally infeasible. We develop an efficient heuristic packing algorithm called TP-heuristic. Allocating a submesh to each task is achieved using the results of packing. We propose two different methods called uniform scaling and non-uniform scaling. Experiments were carried out to test the accuracy of solutions provided by our allocation algorithm.

关键词： parallel processing systems

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architecture-independent workload characterization model for parallel computer architectures

Architecture-independent workload characterization model for...

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Meajil, Abdullah I. El-Ghazawi, Tarek Sterling, Thomas George Washington Univ Washington United States

In this paper, a model is presented for representing and comparing workloads, based on the way they would exercise parallel machines. This workload characterization is derived from parallel instruction centroid and parallel workload similarity. The centroid is a simple measure that aggregates average parallelism, instruction mix, and critical path length. When captured with abstracted information about communication requirements, the result is a powerful tool in understanding the requirements of workloads and their potential performance on target machines. The workload similarity is based on measuring the normalized Euclidean distance (ned) between workload centroids. It will be shown that this workload representation method outperforms comparable ones in accuracy, as well as in time and space requirements. Analysis of the NAS parallel Benchmarks and their performance is presented to demonstrate some of the applications, such as performance prediction with good accuracy, and insight provided by this model.

关键词： parallel processing systems

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Use of feedback in scheduling parallel computations

Use of feedback in scheduling parallel computations

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Dietz, Richard D. Casavant, Thomas L. Andersland, Mark S. Braun, Terry A. Scheetz, Todd E. Univ of Iowa Iowa City United States

This paper discusses the use of run-time feedback for optimizing the execution of parallel computations. Four levels of feedback are distinguished, and the applicability and limitations of each are discussed. A two-part scheduling paradigm known as SEDIA (Static Exploration/Dynamic Instantiation and Activation) that addresses these limitations to perform robust scheduling in the presence of variant run-time behavior is introduced. A key component of this scheduling paradigm is an abstract model of run-time information fidelity, which has evolved from our previous work in the area of Trace Recovery, employing control-theoretic concepts.

关键词： parallel processing systems

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A parallel and fault-tolerant LAN with dual communication subnetworks

A parallel and fault-tolerant LAN with dual communication su...

引用

2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Wang, HQ Yin, ZL Wang, D Department of Computer and Information Science Harbin Engineering of Technology Harbin China

ISBN: (纸本)0818678704

In this paper a parallel and fault-tolerant LAN (P_FTLAN) with dual communication subnetworks is presented to improve LANs' reliability. Its function modes, technical characters, hardware and software architectures and some key, implementation techniques, such as logical addresses and parallel mechanisms, are described in details. Our prototype system and analyzing results suggest that the scheme presented in the paper not only provides an effective approach to high reliable LANs, but also can improve their performance greatly.

关键词： parallel P_FTLAN LAN reliability fault-tolerant dual communication subnetworks

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Finding maximal submeshes in 2D mesh in the presence of failed nodes

Finding maximal submeshes in 2D mesh in the presence of fail...

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Yoo, Seong-Moo Youn, Hee Yong Columbus State Univ Columbus United States

In a parallel computer system with faulty processors, it is highly desirable to reconfigure the system by eliminating the faulty ones and thereby restore the system to some operational state. In the reconfiguration finding the maximum size fault-free subsystem is the main problem. In this paper, we propose an efficient scheme for identifying maximum size fault-free submeshes in a faulty two-dimensional(2D) mesh system. For this, the relations between two submeshes in a 2D mesh have been defined. Then we take two phase approach. In the first phase, an efficient algorithm for determining maximal faulty submeshes in a faulty mesh has been introduced. In the second phase, we have introduced a procedure to identify the maximal fault-free submeshes by splitting all faulty submeshes from a whole mesh. The time complexity of the proposed scheme is O(Nf2) where Nf is the number of faulty processors in a 2D mesh. The proposed scheme can be utilized to the task allocation in 2D meshes in the presence of failed nodes.

关键词： Fault tolerant computer systems

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Dynamic randomized simulation of hierarchical PRAMs on meshes 1

Dynamic randomized simulation of hierarchical PRAMs on meshe...

引用

1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Heywood, Todd Leopold, Claudia Department of Computer Science University of Edinburgh EdinburghEH93J2 United Kingdom Fakultat fur Mathematik und Informatik Friedrich-Schiller-Universitat Jena Jena07740 Germany

ISBN: (纸本)081867038X

The Hierarchical PRAM (H-PRAM) (T. Heywood, S. Ranka, 1992) model is a dynamically partitionable PRAM, which charges for communication and synchronization, and allows parallel algorithms to abstractly represent general locality. We show that the H-PRAM can be implemented efficiently on a two dimensional mesh. We use the Peano indexing scheme to hierarchically partition the mesh. Multiple subPRAMs of the H-PRAM are simulated on irregular submeshes. For an H-PRAM program of cost T, the overall CRCW H-PRAM simulation runs in time constant in T with high probability. The simulation is dynamic, i.e. it does not depend on prior knowledge of a program's specific hierarchical configuration, which may be data dependent. © 1995 IEEE.

关键词： parallel algorithms

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Functionality in ASSY system and language of functional programming 1

Functionality in ASSY system and language of functional prog...

引用

1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Malyshkin, V.E. Supercomputer Software Department Computing Center of Russian Academy of Sciences Novosibirsk630090 Russia

ISBN: (纸本)081867038X

The main features of an integrated system to support the technology of application problem parallelization, development (assembly) of parallel programs, and tuning to available resources of specific multiprocessor system in the course of their execution are presented. Also the notion of functionality is discussed. Contrary to partitioning, the assembly approach supports synthesis (in a broad sense) of the whole problem solution on the basis of elementary ready made fragments. It enable us to use the unified technology for the solution of wide range application problems (in seismic data and image processing, nuclear physics, modeling of natural phenomena etc.) in the framework of the same parallel programming system. This approach is a generalization of our experience in solution of big-size problems. © 1995 IEEE.

关键词： parallel programming

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Methods and tools for the efficient use of parallel computer architectures 1

Methods and tools for the efficient use of parallel computer...

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1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Bode, Arndt Institut für Informatik Lehrstuhl für Rechnertechnik und Rechnerorganisation Technische Universitat Munchen MunchenD-80290 Germany

ISBN: (纸本)081867038X

This article covers research at Technische Universität München on distributed and parallel architectures and applications. First, an overview on the parallel processing research organization is given. The second main topic covers an integrated hierarchical programming environment TOPSYS for parallel and distributed systems developed as part of the research grant. © 1995 IEEE.

关键词： Hierarchical systems

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Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits 2

Combining process algebras and Petri nets for the specificat...

引用

2nd international symposium on Advanced Research in Asynchronous Circuits and Systems

作者： Pena, MA Cortadella, J UNIV POLITECN CATALUNYA DEPT COMP ARCHITECTUREE-08071 BARCELONASPAIN

ISBN: (纸本)0818672986

This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic components previously implemented by skilled designers. However, the generality of the approach often involves the insertion of redundant functionality to the circuit. We propose a new approach based on the composition of Petri nets and the automatic synthesis through Signal Transition Graphs that allows to take advantage of logic synthesis methods to optimize the circuit and make it portable far different delay models and technologies. Some preliminary experimental results have shown the effectiveness of the approach to improve the quality of the circuits. © 1996 IEEE.

关键词： Logic synthesis

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