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共 82 条记录，以下是1-10 订阅

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Intelligent Microbial Growth Monitoring: A parallel OD600 Detection System Based on Artificial Intelligence 2

Intelligent Microbial Growth Monitoring: A Parallel OD600 De...

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2nd International conference on Machine Vision, Image processing and Imaging Technology, MVIPIT 2024

作者： Xu, Libing Ren, Fei Doma, Bonifacio T. Nanjing SuperKong Electronics Co. Ltd. Nan Jing China School of Information Technology Mapua University Philippines School of Graduate Studies Manila Philippines

ISBN: (纸本)9798331543037

Microbial OD600 measurement is a crucial experimental technique in microbiological and molecular biological research, evaluating microbial growth by measuring optical density at 600 nm wavelength. While convenient, this method has limitations. For instance, different microbial species and growth stages may absorb light differently, potentially leading to biases when measuring multiple strains simultaneously. This paper presents an innovative parallel OD600 detection system capable of simultaneously monitoring growth curves of multiple microbial strains. Our research integrates advanced optical systems, precise mechanical control, and artificial intelligence algorithms, not only improving the accuracy and efficiency of bacterial growth measurements but also achieving parallel processing and analysis of multiple samples. We discuss in detail the hardware design, software architecture, and core algorithms, with particular emphasis on the application of machine learning in multi-strain data analysis and prediction. Experimental results demonstrate that this system significantly outperforms traditional methods in measurement accuracy, automation level, multi-sample processing capability, and data analysis. ©2024 IEEE.

关键词： Bacteria

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A parallel Algorithm for the Natural Frequency of Chain Systems on CPU-GPU Heterogeneous Computing Systems 2nd

A Parallel Algorithm for the Natural Frequency of Chain Syst...

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2nd International conference of Mechanical System Dynamics, ICMSD 2023

作者： Peng, Yijia Rui, Xiaoting Wang, Guoping Gu, Junjie Institute of Launch Dynamics Nanjing University of Science and Technology Nanjing China National Key Laboratory of Complex Multibody System Dynamics Nanjing China

ISBN: (纸本)9789819980475

The multibody system transfer matrix method (MSTMM) is a novel dynamic approach which avoids global dynamics equations with a system inertia matrix, utilizes low‐order matrices independent of system degree of freedom, and is highly stylized. With the increase of the number of elements, the time to compute the natural frequency of chain system with the multibody system transfer matrix method is increasing. In order to improve the computational efficiency of the algorithm, an effective way is to parallelize the algorithm. The existing parallel algorithms of using the MSTMM to compute the natural frequency of multibody systems are based on CPU parallel computation, which cannot utilize the GPU of computer, resulting in a waste of computing resources. Therefore, this paper proposes a parallel algorithm for computing the natural frequency of chain systems in CPU-GPU heterogeneous environment. The CUDA parallel computing model is utilized to leverage the computational power of GPUs, while the MPI parallel computing model enables efficient communication and coordination between CPUs and GPUs. The results show that the proposed algorithm is effective, achieving an acceleration ratio 4 times higher than the existing parallel algorithms under the same hardware condition. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Graphics processing unit

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Highly parallel Implementation of Machine Learning algorithms based on Reconfigurable Structures 2

Highly Parallel Implementation of Machine Learning Algorithm...

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2nd International conference on Image processing, Computer Vision and Machine Learning, ICICML 2023

作者： Shi, Yeqiong Wang, Lu Guangxi University of Science and Technology School of Sciences Liuzhou545000 China

ISBN: (纸本)9798350331417

This paper realizes the high parallel hardware acceleration of machine learning and artificial neural networks through resource reuse. This method meets the requirements of the application side for network diversification, processing performance, high resource utilization, and low power consumption. In this experiment, strong real-time and high energy efficiency parallel intensive computing at the TOPS level of the machine learning algorithm is realized, and the performance of neural network terminal reasoning is significantly improved. In this paper, 10 AI modules are tested according to the proposed parallel processing architecture, and the classification results of 10 experiments for each module are plotted. It can be seen from the results that after repeated tests, the model classification accuracy of the module can be steadily improved, among which the expert group has improved by about 20%, and the general group has improved by about 27%. In addition, the application of deep neural network compression technology in artificial intelligence processors needs to focus on solving the balance between high compression ratio and low precision loss and between irregular clipping and high parallel computing efficiency. © 2023 IEEE.

关键词： Artificial intelligence Computers science hardware acceleration Machine learning parallel computing

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2nd NIELIT's International conference on Communication, Electronics and Digital Technologies, NICEDT 2024

2nd NIELIT's International Conference on Communication, Elec...

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2nd NIELIT's International conference on Communication, Electronics and Digital Technologies, NICEDT 2024

ISBN: (纸本)9789819736003

The proceedings contain 79 papers. The special focus in this conference is on Communication, Electronics and Digital Technologies. The topics include: Design and Development of parallel Beamformer Model for RTL Verification;early Detection of Oral Cancer Using Image processing and Computational Techniques;loRa Enabled IoT Sensor Framework for Monitoring Urban Flood in Guwahati City;study and Implementation of Smart Positioner Prototype for Industrial Applications;tactile Internet: A Next Gen IoT Technology;a Deep Learning Approach for hardware Trojan Detection in Netlist of Integrated Circuits with Graph Neural Networks;a Comparative Study of Jpeg and Similar Compression Standards for Wireless Communication;iot-Based Transport Monitoring System for Pharmaceutical Industry;non-intrusive Remote Apiculture Monitoring System;design and Analysis of Enhanced Bandwidth Slotted Logarithmic Spiral Patch Antenna for 5G Communication;IoT Based Real-Time Automatic Number Plate Detection Using OpenCV;prompt Engineering for the Automated Generation of Weaving Pattern;blood Disease Detection System Based on Haemogram Report Using Decision Tree Algorithm;Development of SPR Sensor-Based System for Copper Ion Detection in Water;generation of YuBraj Twist and YuBrajTwest Weaves;maintenance and Performance of Solar Water Pump in a Rural Agricultural Community: A Case Study;integrative Analysis of Cancer Gene Expression Using Bio-Inspired algorithms and Machine Learning: Identification of Key Genes;Potential of AI in Pharma: Bridge the Gap Between Data and Therapeutics;A PC-Based Ultrasound Color Doppler Performance Improvement Using Intel® IPPs;Deep Reach Centrality: An Innovative Network Centrality Metric Grounded in Distance and Degree, with Its Performance Analysis Applied to the SARS-CoV-2 Protein–protein Interaction Network.

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2nd NIELIT's International conference on Communication, Electronics and Digital Technologies, NICEDT 2024

2nd NIELIT's International Conference on Communication, Elec...

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2nd NIELIT's International conference on Communication, Electronics and Digital Technologies, NICEDT 2024

ISBN: (纸本)9789819736034

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RESEARCH ON HIGH-SPEED MOTOR CONTROL BASED ON FPGA And SEMI-PHYSICAL SIMULATION

RESEARCH ON HIGH-SPEED MOTOR CONTROL BASED ON FPGA AND SEMI-...

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2024 CSAA/IET International conference on Aircraft Utility Systems, AUS 2024

作者： Wang, Xinyuan Sun, Lili Zhang, Run AVIC Shaanxi Aero Electric Co. Ltd No. 17 Jinye 2nd Road Xi’an China

With the advancement of more electric aircraft, the Environmental Control System (ECS) has progressively shifted from the traditional engine bleed mode to an electric drive mode. This transition not only significantly simplifies the aircraft's structure but also effectively reduces pollutant emissions. At the heart of the Electric ECS (EECS), the High-Speed Permanent Magnet Synchronous Motor (HSPMSM) stands out for its exceptional performance, with each rotation cycle requiring mere milliseconds or less. To ensure the stable operation of the HSPMSM at such high speeds, the design of its control system faces formidable challenges, particularly stringent requirements on control cycle times and latency. In response, this paper proposes an architecture integrating FPGA and DSP for precise HSPMSM control, aiming to significantly enhance the response speed of the control system. Within the control strategy for the HSPMSM, we innovatively incorporate advanced functional module designs such as the Coordinate Rotation Digital Computer (CORDIC) algorithm, Proportional-Integral (PI) controllers, and Space Vector Pulse Width Modulation (S VPWM) by using the powerful parallel processing capabilities of FPGA. Compared with traditional controllers like DSP for HSPMSM applications, the successful integration of FPGA with advanced control algorithms can effectively shorten the control cycle. Besides, by constructing a hardware-in-the-loop (HIL) real-time simulation model, we successfully demonstrated the remarkable advantages of the FPGA-based control system in terms of real-time performance, stability, and control accuracy. © The Institution of Engineering & Technology 2024.

关键词： hardware-in-the-loop simulation

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Research on Chip Level Inspection and Maintenance System of Electronic Products under Computer Digitization

Research on Chip Level Inspection and Maintenance System of ...

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Electrical Engineering, Big Data and algorithms (EEBDA), IEEE International conference on

作者： Huifen Sun Information Engineering Department Zhenjiang Branch of Jiangsu Union Technical Institute Zhenjiang China

In this paper, a fixed fault model is established, and a digital chip tester is designed with HT46RU24 as the core. The FPGA+SDRAM high performance hardware processing platform is built according to the high efficiency of FPGA parallel processing. Using Quartus II software and Verilog HDL hardware description language to write a program to detect the edge of chip pins. In this paper, a chip detection algorithm based on generalized Hough transform is proposed to reduce the computational complexity. The main idea of this algorithm is to combine multi-scale analysis with generalized Hough transform. The algorithm is applied to the chip detection of automatic optical detection system. Then the system controls and tests the operation of the hardware through the test code and compares the test results with the exact values. The simulation results show that the system can automatically give the result of right or wrong judgment.

关键词： Software design Simulation Software algorithms Transforms parallel processing hardware Software

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Implementation of FPGA-based hardware acceleration system for U-Net networks

Implementation of FPGA-based hardware acceleration system fo...

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Electrical Engineering, Big Data and algorithms (EEBDA), IEEE International conference on

作者： Peng Chen Liqiang Xu Wuhan University of Science and Technology Wuhan China

In recent years, with the rapid development of network technology in our country, neural network algorithm is widely recognized and applied to image. U-Net is one of them, which can effectively improve the efficiency of FPGA network hardware utilization, and thus enhance the acceleration system. The main principle of the U-Net is to accelerate the speed of convolutional computation by means of circular flow and circular unfolding, and to improve the performance of the network hardware. In order to learn more about it, this paper will discuss the relevant research.

关键词： Electrical engineering Constraint optimization Image recognition Neural networks parallel processing Big Data hardware acceleration

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High-Speed Data Transfer using AXI Protocol for Image Detection

High-Speed Data Transfer using AXI Protocol for Image Detect...

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Innovation in Technology (INOCON), IEEE International conference for

作者： Rajat Raj Sharat Kumar Miskin Naman Bhatia Electronics and Communication Engineering RV College of Engineering Bengaluru India

Convolutional neural networks (CNN) due to their excellent accuracy, have emerged as the leading machine learning method. However, it becomes difficult to deploy CNN algorithms on hardware platforms because of their high memory bandwidth, computational complexity, and power consumption. hardware accelerators such as Field Programmable Gate Arrays (FPGA), Graphics processing Unit (GPU), etc. are excellent platforms for modelling CNN algorithms. The purpose of the paper is to run a standard software process in hardware and exploit natural parallelism in hardware to speed up neural network prediction. The paper presents a rule-based synthesizable Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocol for high-speed data transmission. The paper develops a computer vision system on an FPGA that could recognize the numbers 0 through 9 written by hand for the capstone design project. The findings show that 91% accuracy is achieved through Rectified linear activation unit (ReLU) which can be increased to 98% by implementing the Sigmoid activation function with a depth of 10 bits. The method provides good accuracy and clock performance while using few resources.

关键词： Protocols Machine learning algorithms Computational modeling Software algorithms Neural networks Graphics processing units parallel processing

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Design and Analysis of Efficient On-Star Compression algorithms for FPGA Platforms

Design and Analysis of Efficient On-Star Compression Algorit...

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Computer, Vision and Intelligent Technology (ICCVIT), International conference on

作者： Guoliang Zhang Xueying Wang Jianpeng Fan College of Electronic Science and Technology National University of Defense Technology Changsha China

ISBN: (数字)9798331540043

ISBN: (纸本)9798331540050

Image compression has always been a hot topic in the field of aerospace. The onboard processing unit, due to its background of deep space operation, has greatly limited performance in terms of data storage and data transmission. Satellite remote sensing images are developing towards larger size, higher frame frequency, and more frequency bands, which increasingly demand storage space and processing power. There is an urgent need for a set of efficient and lightweight image compression hardware and software. Therefore, in this work, we have improved the Context-Based Adaptive Lossless Image Compression (CALIC) algorithm, including error quantization and entropy coding, to meet the requirements for on-orbit processing in terms of compression time and compression ratio. At the same time, aiming at the working scenario of on-orbit processing, we chose Field-Programmable Gate Array (FPGA) as the platform to deploy the improved CALIC and designed the arithmetic coding Av value calculation process in parallel on this basis, which greatly reduced the processing time on the hardware side. We have carried out simulation verification of this paper’s image compression algorithm on the KODAK24 and SZTAKI_Airchange datasets. The experimental results show that our method strikes a good balance between compression ratio and compression rate compared with typical compression algorithms, making it suitable for on-orbit processing scenarios.

关键词： Technological innovation Image coding Quantization (signal) Software algorithms hardware Software Field programmable gate arrays Remote sensing Compression algorithms Arithmetic

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