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Toward A New Approach for Massive LiDAR Data processing 2

Toward A New Approach for Massive LiDAR Data Processing

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2nd IEEE International conference on Spatial Data Mining and Geographical Knowledge Services (ICSDM)

作者： Cao, V-H. Chu, K-X. Le-Khac, N-A. Kechadi, M-T. Laefer, D. Truong-Hong, L. Univ Coll Dublin Sch Comp Sci & Informat Dublin 4 Ireland Univ Coll Dublin Sch Civil Struct & Environm Engn Dublin 4 Ireland

ISBN: (纸本)9781479977499

Laser scanning (also known as Light Detection And Ranging) has been widely applied in various application. As part of that, aerial laser scanning (ALS) has been used to collect topographic data points for a large area, which triggers to million points to be acquired. Furthermore, today, with integrating full wareform (FWF) technology during ALS data acquisition, all return information of laser pulse is stored. Thus, ALS data are to be massive and complexity since the FWF of each laser pulse can be stored up to 256 samples and density of ALS data is also increasing significantly. processing LiDAR data demands heavy operations and the traditional approaches require significant hardware and running time. On the other hand, researchers have recently proposed parallel approaches for analysing LiDAR data. These approaches are normally based on parallel architecture of target systems such as multi-core processors, GPU, etc. However, there is still missing efficient approaches/tools supporting the analysis of LiDAR data due to the lack of a deep study on both library tools and algorithms used in processing this data. In this paper, we present a comparative study of software libraries and new algorithms to optimise the processing of LiDAR data. We also propose new method to improve this process with experiments on large LiDAR data. Finally, we discuss on a parallel solution of our approach where we integrate parallel computing in processing LiDAR data.

关键词： LiDAR data parallel processing Kd-tree TreeP

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A hardware Structure of HEVC Intra Prediction

A Hardware Structure of HEVC Intra Prediction

引用

International conference on Information Science and Control Engineering (ICISCE)

作者： Wei Lu Ningmei Yu Jianghan Nan Dongfang Wang Department of Electronics Engineering Xi'an University of Technology Xi'an China

ISBN: (纸本)9781467368513

In this paper a parallel hardware structure of ASIC for HEVC intra prediction encoding is proposed. This structure by analyzing software algorithm, according to the characteristics of the ASIC implementation of parallelization, designs the DC, a planar, horizontal and vertical Angle prediction hardware structure of the parallel processing, and finished the calculation of SATD. A parallel prediction hardware structure is designed in order to improve the computational efficiency. SATD calculated using a set of registers in the shift and 4-2 compression method implements the pipeline of processing, greatly improving the throughput rate and computational efficiency. After logic synthesis using the SMIC0.13μm standard cell library, simulation results show that the proposed architecture of 4×4 logic gates for 29.8K, on-chip cache to 6.8 KB. At 300MHz, real-time processing 3840×2160@25fps sequence of images, extremely suit for VLSI HD encoder.

关键词： Image coding hardware Registers Prediction algorithms Arrays Very large scale integration Encoding

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Recognition of Access Patterns for DSP Kernel Codes 2

Recognition of Access Patterns for DSP Kernel Codes

引用

2nd International conference on Systems and Informatics (ICSAI)

作者： Li, Xiaoyang Liu, Yu Gong, Chen Liu, Dake Beijing Inst Technol Lab Applicat Specif Instruct Set Proc Beijing 100081 Peoples R China

ISBN: (纸本)9781479954582

Kernel-stream programming is a state-of-the-art method to program on parallel Digital Signal processing (DSP) platforms. As the most legacy programs are written in sequential languages, a challenge of kernel-stream programming is to automatically recognize kernel code patterns and replace them with hardware optimized parallel library codes. In this paper, we try to solve an essential problem of kernel code recognition: the memory access patterns of matrix kernel codes. Though it is essential, most kernel recognizers previously did not recognize memory access patterns, simply recognizing only custom templates instead. We define eight 1-dimensional and 2 dimensional array access patterns frequently used in matrix kernel computing. The recognition algorithm is implemented in LLVM compiler infrastructure and is tested against several matrix kernels. Results show much improved matrix codes matches based on using our predefined access patterns. As modeling of access patterns in this paper is close to their original mathematical representations, limited number of kernel templates is needed to successfully complete recognitions of our interested matrix algorithms.

关键词： memory access pattern scalar evolution parallel programming compiler

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Folded FFT architecture for real-valued signals based on Radix-23 algorithm

Folded FFT architecture for real-valued signals based on Rad...

引用

International conference on Devices, Circuits and Systems (ICDCS)

作者： Pradnya Zode Abhilesh Thor A. Y. Deshmukh Dept. of Electronics Engg. YCCE Nagpur India Deptt. Of Electronic Engg. GHRCE Nagpur India

A new FFT architecture for real-valued signal is proposed using Radix-2 3 algorithm. It is based on modifying flow graph of the FFT algorithm such that it has both real and complex datapaths. A redundant operation in flow graph is replaced by imaginary part. Using folding technique RFFT architecture with any level of parallelism can be achieved. This RFFT architecture will lead to low hardware complexity as compare to radix-2 and radix 22 algorithm in terms of adder, multiplier and delay. N-point 2 parallel radix-2 3 architecture requires (log 8 N-) complex multiplier, 2log 2 N adders, 3N/2-2 delays. RFFT which is used for real time applications and in portable devices for which low power consumption is main requirement, so accordingly carry propagate adder which has least power consumption and CSD multiplier is selected for our proposed architecture.

关键词： Computer architecture Adders Delays Signal processing algorithms Power demand hardware Flow graphs

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Recognition of access patterns for DSP kernel codes

Recognition of access patterns for DSP kernel codes

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International conference on Systems and Informatics (ICSAI)

作者： Xiaoyang Li Yu Liu Chen Gong Dake Liu Lab of Application Specific Instruction-set Processors Beijing Institute of Technology Beijing China

ISBN: (纸本)9781479954599

Kernel-stream programming is a state-of-the-art method to program on parallel Digital Signal processing (DSP) platforms. As the most legacy programs are written in sequential languages, a challenge of kernel-stream programming is to automatically recognize kernel code patterns and replace them with hardware optimized parallel library codes. In this paper, we try to solve an essential problem of kernel code recognition: the memory access patterns of matrix kernel codes. Though it is essential, most kernel recognizers previously did not recognize memory access patterns, simply recognizing only custom templates instead. We define eight 1-dimensional and 2-dimensional array access patterns frequently used in matrix kernel computing. The recognition algorithm is implemented in LLVM compiler infrastructure and is tested against several matrix kernels. Results show much improved matrix codes matches based on using our predefined access patterns. As modeling of access patterns in this paper is close to their original mathematical representations, limited number of kernel templates is needed to successfully complete recognitions of our interested matrix algorithms.

关键词： Decision support systems Lead conferences Informatics parallel programming Program processors Radio frequency

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Massively parallel Suffix Array Queries and On-Demand Phrase Extraction for Statistical Machine Translation Using GPUs 2

Massively Parallel Suffix Array Queries and On-Demand Phrase...

引用

2nd Workshop on Computational Linguistics for Literature, CLfL 2013 at the 2013 conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, NAACL-HLT 2013

作者： He, Hua Lin, Jimmy Lopez, Adam Dept. of Computer Science University of Maryland College ParkMD United States iSchool and UMIACS University of Maryland College ParkMD United States HLTCOE Johns Hopkins University BaltimoreMD United States

ISBN: (纸本)9781937284473

Translation models in statistical machine translation can be scaled to large corpora and arbitrarily-long phrases by looking up translations of source phrases "on the fly" in an indexed parallel corpus using suffix arrays. However, this can be slow because on-demand extraction of phrase tables is computationally expensive. We address this problem by developing novel algorithms for general purpose graphics processing units (GPUs), which enable suffix array queries for phrase lookup and phrase extraction to be massively parallelized. Compared to a highly-optimized, state-of-the-art serial CPU-based implementation, our techniques achieve at least an order of magnitude improvement in terms of throughput. This work demonstrates the promise of massively parallel architectures and the potential of GPUs for tackling computationally-demanding problems in statistical machine translation and language processing. © 2013 Association for Computational Linguistics.

关键词： Graphics processing unit

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A GPU-Based parallel processing Method for Slope Analysis in Geographic computation'

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2nd International conference on Advanced Engineering Materials and Technology (AEMT)

作者： Lv Minhui Xiong Wei Cai Lei Huazhong Univ Sci & Technol Shchool Management Wuhan 430074 Peoples R China Naval Univ Engn Dept Equipment Econ & Management Wuhan 430033 Peoples R China Natl Univ Def Technol Coll Elect Sci & Engn Changsha 410073 Peoples R China

ISBN: (纸本)9783037854471

Nowadays, geographical computation presents to be distributed, parallel, and diversification application trend. Influence of problem scale and response speed requirement received more attention. And high performance computational systems, such as "TianHe 1-A", provides a new generation of hardware supports. In order to make full use of these high performance computational resources, appropriate and efficient parallel algorithms are needed. New parallel computing optimization technique of the geography is proposed in this paper by designing new parallel algorithms for slope analysis. We implement it based on CUDA. Experimental results with random DEM data in uniform distribution validate our methods.

关键词： graphic processing unit (GPU) parallel computing slope analysis CUDA

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Hybrid reconfigurable PC add-on card for parallel image processing

Hybrid reconfigurable PC add-on card for parallel image proc...

引用

2nd International conference on Mechanical and Aerospace Engineering (ICMAE 2011)

作者： Ravi, Aadithya Moorthy, Easwara E. A. Vidya, D. Kumar, G. Mahesh Anna Univ Coll Engn Madras 600025 Tamil Nadu India iNautix Technol India Pvt Ltd Learning & Dev Madras Tamil Nadu India S V C E Elect & Elect Engn EEE Madras Tamil Nadu India

ISBN: (纸本)9783037852620

Specific hardware solutions are always faster than programmable architectures. But dedicated architectures have the inherent disadvantage of inflexibility. Changes in the algorithm or extensions of the application are handled easily by programmable architectures. The approach discussed here involves a hardware-software co-design to optimize on performance and programmability. The architecture houses two SHARC processors to aid in parallelizing the image processing algorithms, and a reconfigurable FPGA which may be configured on the fly to execute any of the real-time algorithms as desired. The functional memory would consist of pre-designs (FPGA based) of certain objects, each of which could be used to configure an FPGA to perform a particular function.

关键词： Architecture co-design image processing hardware-reconfigurability

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A two stage parallel encoder scheme for real time video encoder

A two stage parallel encoder scheme for real time video enco...

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2012 2nd IEEE International conference on Signal processing, Communications and Computing, ICSPCC 2012

作者： Dong, Shengfu Wang, Zhihang Wang, Ronggang Wang, Zhenyu Gao, Wen School of Computer and Information Engineering Peking University Shenzhen Graduate School Shenzhen 518055 China School of Electronics Engineering and Computer Science Peking University Beijing 100871 China

ISBN: (纸本)9781467321938

With the development of hardware technologies, multi-core processor becomes more and more popular. At the same time, the performance of video encoding technologies is greatly improved at the cost of complexity. How to exploit the computing capacity of the multi-core processors efficiently to meet the demand of video encoding technology is a challenging task. Traditional work usually split the frame into slices to enable parallel encoding. But the coding efficiency will lose especially when there are more slices. In this paper, first we propose a two stage real time encoding scheme without splitting the frame into slices. Secondly, some modules in the hybrid video coding scheme, such as interpolation and loop filter, are split into independent modules that can be processed in parallel. A simple and effective task scheduling strategy is also proposed to fully exploit the CPU capacity. Finally, fast algorithms suitable for this architecture are developed. Experimental results show that we can encode the 720p sequence at about 50 fps with little loss in the rate distortion performance. © 2012 IEEE.

关键词： Video signal processing

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Image parallel processing Based on GPU

Image Parallel Processing Based on GPU

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2nd IEEE International conference on Advanced Computer Control

作者： Zhang, Nan Wang, Jian-li Chen, Yun-shan Chinese Acad Sci Grad Sch Changchun Inst Opt Fine Mech & Phys Changchun Peoples R China Chinese Acad Sci Changchun Inst Opt Fine Mech & Phys Changchun Peoples R China

ISBN: (纸本)9781424458479

In order to solve the compute-intensive character of image processing, based on advantages of GPU parallel operation, parallel acceleration processing technique is proposed for image. First, efficient architecture of GPU is introduced that improves computational efficiency, comparing with CPU. Then, Sobel edge detector and homomorphic filtering, two representative image processing algorithms, are embedded into GPU to validate the technique. Finally, tested image data of different resolutions are used on CPU and GPU hardware platform to compare computational efficiency of GPU and CPU. Experimental results indicate that if data transfer time, between host memory and device memory, is taken into account, speed of the two algorithms implemented on GPU can be improved approximately 25 times and 49 times as fast as CPU, respectively, and GPU is practical for image processing.

关键词： Image processing parallel operation GPU CUDA

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