检索结果-内蒙古大学图书馆

An area-efficient bit-serial integer and GF(2") multiplier

MICROELECTRONIC ENGINEERING 2007年第2期84卷 253-259页

作者： Schimmler, Manfred Schmidt, Bertil Lang, Hans-Werner Heithecker, Sven Nanyang Technol Univ Sch Comp Engn Singapore 63798 Singapore Univ Kiel Inst Informat D-24118 Kiel Germany Univ Appl Sci Fachhosch Flensburg D-24943 Flensburg Germany Tech Univ Carolo Wilhelmina Braunschweig Inst Datentech & Kommun D-38106 Braunschweig Germany

This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers as well as for multiplication in finite fields of order 2". It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Systolic Array (ISA) parallel computer model [M. Kunde, H.W. Lang, M. Schimmler, H. Schmeck, H. Schroder, parallel Computing 7 (1988) 25-39, H.W. Lang, Integration, the VLSI Journal 4 (1986) 65-74]. The multiplier operates least significant bit (LSB)-first for integer multiplication and most significant bit ( )-first for finite field multiplication. It is a modular bit-serial design, which on the one hand can be efficiently implemented in hardware and on the other hand has the advantage that it can handle operands of arbitrary length. (c) 2006 Elsevier B.V. All rights reserved.

关键词： bit-serial multiplier two's-complement multiplication finite field multiplication instruction systolic array long operand arithmetic

来源：评论

学校读者我要写书评

暂无评论

K-Project / first step: To improve data manipulations and representations on parallel computers 2nd

K-Project / first step: To improve data manipulations and re...

引用

2nd Joint International conference on Vector and parallel processing, conpar 1992

作者： Essafi, Hassane Pic, Marc Juvin, Didier Commissariat à l’Energie Atomique C.E.N. Saclay DTA/DEIN/SLA Gif-sur-Yvette Cedex91191 France

ISBN: (纸本)9783540558958

Large array processing can be done efficiently by a linear processor array. We developed a SIMD line-processor computer and a high-level programmation’s environment including a C-like Array Programming Language with Object-Oriented abilities in order to compute physical problems. We based our work on the problem of manipulation, high-level representation and machine-level mapping of data. We try to find hardware and software solutions to provide an easy way to program parallel computer and an efficient use of SIMD parallelism. © Springer-Verlag Berlin Heidelberg 1992.

关键词： Array processing

来源：评论

学校读者我要写书评

暂无评论

High Speed Pattern Matching in Genetic Data Base with Reconfigurable hardware

High Speed Pattern Matching in Genetic Data Base with Reconf...

引用

2nd International conference on Intelligent Systems for Molecular Biology, ISMB 1994

作者： Lemoine, Eric Quinqueton, Joel Sallantin, Jean Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier UMR 9928 Université Montpellier II/CNRS 161 rue ADA Cedex 5 Montpellier34392 France

ISBN: (纸本)0929280687

Homology detection in large data bases is probably the most time consuming operation in molecular genetic computing systems. Moreover, the progresses made all around the world concerning the mapping and sequencing of the genome of Homo Sapiens and other species have increased the size of data bases exponentially. Therefore even the best workstation would not be able to reach the scanning speed required. In order to answer this need we propose an algorithm, A2R2, and its implementation on a massively parallel system. Basically, two kinds of algorithms are used to search in molecular genetic data bases. The first kind is based on dynamic programming and the second on word processing, A2R2 belongs to the second kind. The structure of the motif (pattern) searched by A2R2 can support those from FAST, BLAST arid FLASH algorithms. After a short presentation of the reconfigurable hardware concept and technology used in our massively parallel accelerator we present the A2R2 implementation. This parallel implementation outperforms any kind of previously published genetic data base scanning hardware or algorithms. We report up to 25 million nucleotides per scanning seconds as our best results. © 1994, AAAI (***). All rights reserved.

关键词： Dynamic programming

来源：评论

学校读者我要写书评

暂无评论

Visualizing high-level communication and synchronization

Visualizing high-level communication and synchronization

引用

1996 IEEE 2nd International conference on algorithms and Architectures for parallel processing (ICA3PP 96)

作者： Hofman, R Langendoen, K Bal, H Vrije Universiteit Amsterdam Amsterdam Netherlands

ISBN: (纸本)0780335295

High-level parallel languages ease writing of parallel programs. However, since they deepen the gap between language and underlying hardware, performance debugging is hard. It is essential to use tools that present the user with performance data at the language level. Besides this, for hard performance problems it is necessary to be able to descend into the software hierarchy. A trace package and a viewing tool, orcshot, are presented that address these issues for the high-level parallel language Orca. Communication and synchronization are done with ''shared data objects'', and the tool visualizes traces in relation to these objects. Orcshot possesses a powerful filter utility to achieve the necessary data reduction. Orcshot can be adapted to other object-based languages with slight effort. The orcshot performance visualization tool has already helped find numerous performance bugs. One example is presented.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

hardware implementation of windowing in a multicast packet switch

Hardware implementation of windowing in a multicast packet s...

引用

Proceedings of the 1996 IEEE 2nd International conference on algorithms & Architectures for parallel processing, ICA3PP

作者： Pinnu, Madhusudhana R. Sharma, Neeraj K. La Trobe Univ Melbourne

In a banyan based broadband packet switch using input queuing, the throughput of the switch is limited by the head of line blocking. Head of line blocking prevents packet in the input buffer from accessing an available output port in the network since the packet ahead of it in the buffer is blocked. Windowing is a technique used to mitigate the head of line blocking by relaxing the strict first-in-first-out queuing discipline of the input buffers. In this paper, we present a hardware implementation of windowing for a multicast packet switch. This implementation is further extended to include cyclic priority discipline to insure fairness among the input ports.

关键词： Packet switching

来源：评论

学校读者我要写书评

暂无评论

FPGA hardware Architecture for Stereoscopic Image Compression Based on Block Matching, Watermarking and Hamming Code 2

FPGA Hardware Architecture for Stereoscopic Image Compressio...

引用

2nd International conference on Image processing, Applications and Systems (IPAS)

作者： Akkad, Ghattas ElHassan, Moustapha Ayoubi, Rafic Univ Balamand Comp & Elect Engn Koura Lebanon

ISBN: (纸本)9781509016457

Image compression and size reduction increases the number of images stored on a memory space and reduces bandwidth consumption while increasing transmission speed on a communication channel. Images can be compressed and decompressed using different methods and algorithms. With the vast increase of quality and size, dedicated processors with parallel processing blocks such as FPGAs are mainly targeted to implementing faster processing circuits and algorithms. This paper proposes FPGA hardware architecture for a stereoscopic image compression algorithm based on block matching, watermarking and Hamming code.

关键词： MSB FPGA Stereoscopic image compression watermarking Hamming Code

来源：评论

学校读者我要写书评

暂无评论

Hmesh: A vlsi architecture for parallel processing 2nd

引用

2nd conference on algorithms and hardware for parallel processing, conpar 1986

作者： Raghavendra, C.S. Electrical Engineering-Systems Department University of Southern California Los AngelesCA90089-0781 United States

ISBN: (纸本)9783540168119

Enhancements to array processors in the form of broadcast buses have been proposed for improving the speeds of algorithms in linear algebra, image processing and computational geometry. In this paper, we consider certain practical issues in such arrays which include fewer processors connected to the broadcast buses and finite time, namely log N time for broadcasting data to N processors. We propose a modified broadcast bus VLSI architecture which consists of a √N × √N mesh connected structure and a hierarchy of broadcast buses in each row and in each column such that every bus has k PE's. That is, in any row or column, in the first level there are √N/k buses with groups of k PE's connected to each bus. One PE from each of this group is connected to second level of buses in a similar manner. This is recursively done until there are only k PE's left which are connected by a broadcast bus. With this architecture, maximum, minimum, or sum of N values can be found in O(log N), median row of a binary picture in O(log N), shortest distance between two points in O(log N). This architecture is well suited for parallel processing of applications in Linear Algebra, Image processing, Computational Geometry and Numerical Computations. These restricted connections to buses reduces the I/O ports significantly, and therefore, is more suitable for VLSI implementation. © 1986, Springer-Verlag.

关键词： Computational geometry

来源：评论

学校读者我要写书评

暂无评论

A GPU-Based parallel processing Method for Slope Analysis in Geographic computation'

A GPU-Based Parallel Processing Method for Slope Analysis in...

引用

2nd International conference on Advanced Engineering Materials and Technology (AEMT)

作者： Lv Minhui Xiong Wei Cai Lei Huazhong Univ Sci & Technol Shchool Management Wuhan 430074 Peoples R China Naval Univ Engn Dept Equipment Econ & Management Wuhan 430033 Peoples R China Natl Univ Def Technol Coll Elect Sci & Engn Changsha 410073 Peoples R China

ISBN: (纸本)9783037854471

Nowadays, geographical computation presents to be distributed, parallel, and diversification application trend. Influence of problem scale and response speed requirement received more attention. And high performance computational systems, such as "TianHe 1-A", provides a new generation of hardware supports. In order to make full use of these high performance computational resources, appropriate and efficient parallel algorithms are needed. New parallel computing optimization technique of the geography is proposed in this paper by designing new parallel algorithms for slope analysis. We implement it based on CUDA. Experimental results with random DEM data in uniform distribution validate our methods.

关键词： graphic processing unit (GPU) parallel computing slope analysis CUDA

来源：评论

学校读者我要写书评

暂无评论

Recognition of Access Patterns for DSP Kernel Codes 2

Recognition of Access Patterns for DSP Kernel Codes

引用

2nd International conference on Systems and Informatics (ICSAI)

作者： Li, Xiaoyang Liu, Yu Gong, Chen Liu, Dake Beijing Inst Technol Lab Applicat Specif Instruct Set Proc Beijing 100081 Peoples R China

ISBN: (纸本)9781479954582

Kernel-stream programming is a state-of-the-art method to program on parallel Digital Signal processing (DSP) platforms. As the most legacy programs are written in sequential languages, a challenge of kernel-stream programming is to automatically recognize kernel code patterns and replace them with hardware optimized parallel library codes. In this paper, we try to solve an essential problem of kernel code recognition: the memory access patterns of matrix kernel codes. Though it is essential, most kernel recognizers previously did not recognize memory access patterns, simply recognizing only custom templates instead. We define eight 1-dimensional and 2 dimensional array access patterns frequently used in matrix kernel computing. The recognition algorithm is implemented in LLVM compiler infrastructure and is tested against several matrix kernels. Results show much improved matrix codes matches based on using our predefined access patterns. As modeling of access patterns in this paper is close to their original mathematical representations, limited number of kernel templates is needed to successfully complete recognitions of our interested matrix algorithms.

关键词： memory access pattern scalar evolution parallel programming compiler

来源：评论

学校读者我要写书评

暂无评论

Fast ARFTIS Reconstruction algorithms Using CUDA

Fast ARFTIS Reconstruction Algorithms Using CUDA

引用

2nd International conference on High Performance Computing and Applications

作者： Cui, Deqi Liao, Ningfang Wu, Wenmin Tan, Boneng Lin, Yu Beijing Inst Technol Dept Opt & Elect Engn Beijing 100081 Peoples R China

ISBN: (纸本)9783642118418

In order to realize the fast reconstruction processing of all-reflective Fourier Transform Imaging Spectrometer (ARFTIS) data, the authors implement reconstruction algorithms on GPU using Compute Unified Device Architecture (CUDA). We use both CUDA IDFFT library and customization CUDA parallel kernel to accelerate the spectrum reconstruction processing of ARFTIS. The results show that the CUDA can drive hundreds of processing elements ('many-core' processors) of GPU hardware and can enhance the efficiency of spectrum reconstruction processing significantly. Farther, computer with CUDA graphic cards will implement real-time data reconstruction of ARFTIS alone.

关键词： ARFTIS Reconstruction CUDA parallel

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：