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conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

作者： Ogoubi, Etienne David, Jean Pierre Université de Montréal

ISBN: (纸本)0780383222

Reconfigurable systems now offer tens of millions equivalent gates, allowing highly parallel processing impossible to reach with general purpose processors. Nevertheless, designing a circuit is intrinsically more complicated than a software approach because space and time concepts must be considered together. Current HDLs, which use a low level description, are only accessible to highly qualified hardware designers and require much more time than a pure software solution. This paper demonstrates how the use of higher level HDL allows people with a software background to design complex architectures in a simple and efficient way. Five sort algorithms have been designed and tested in a few days using our intermediate level HDL. Results show that the design time, circuit space and global performances are at least one order of magnitude better than a processor approach for a NoC and could easily go to three orders of magnitude. © 2004 IEEE.

关键词： Computer hardware description languages

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Design of a processing element of a SIMD computer for genetic algorithms

Proceedings of the Conference on High Performance Computing ...

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Proceedings of the conference on High Performance Computing on the Information Superhighway, HPC Asia'97 1997年 688-691页

作者： Inoue, Tomio Sano, Masahiko Takahashi, Yoshizo Univ of Tokushima Tokushima Japan

We have been investigating the efficiency of Genetic algorithms (GA) for solving for a variety of real problems. During our investigations we have concluded that the large amount computational time required to find GA based solutions on conventional computers is restrictive. We are therefore developing an innovative new computer architecture, suitable for the solution of large scale problems using GAs. In this paper we introduce the SIMD-GA (Single Instruction stream Multiple Data stream Genetic Algorithm), and discuss its hardware design and implementation. By taking advantage of the recent advances is HDLs (hardware Description Language) and FPGA's (Field Programmable Gate Array) we have been able to quickly develop and prototype a PE (processing Element) for a SIMD-GA. This approach allows us to build a cost-effective parallel processing architecture to overcome the problem of the computational time required for traditional sequential GA implementation.

关键词： parallel processing systems

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AQuES: an agent-based query evaluation system

AQuES: an agent-based query evaluation system

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International conference on Cooperative Information Systems

作者： M. Stillger J.K. Obermaier J.C. Freytag Institut fur Informatk Humboldt-Universitaet zu Berlin Germany

Optimization for distributed and parallel database systems is an overly complex problem. This complexity arises due to the various kinds of parallelism and the coexistence of heterogeneous hardware modules. The query optimizers for those systems must exploit parallel algorithms for algebra operators, independent data parallelism and resource scheduling. In addition, unexpected deviations of the workload at runtime enforce new, dynamic execution strategies. This paper reports ongoing work in developing an agent-based query optimization and execution system to cope with this problem. It is based on the principles of distributed, symmetric processes which work in a cooperative, yet independent manner. This approach enables a dynamical adaptation to changes in the execution environment with local and simple actions. We present the architecture of the components and outline the principle of distributed query execution within this software system.

关键词： Query processing Database systems hardware Runtime parallel algorithms Power system modeling Distributed databases Job shop scheduling Computer architecture Software systems

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Visualizing high-level communication and synchronization

Visualizing high-level communication and synchronization

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1996 IEEE 2nd International conference on algorithms and Architectures for parallel processing (ICA3PP 96)

作者： Hofman, R Langendoen, K Bal, H Vrije Universiteit Amsterdam Amsterdam Netherlands

ISBN: (纸本)0780335295

High-level parallel languages ease writing of parallel programs. However, since they deepen the gap between language and underlying hardware, performance debugging is hard. It is essential to use tools that present the user with performance data at the language level. Besides this, for hard performance problems it is necessary to be able to descend into the software hierarchy. A trace package and a viewing tool, orcshot, are presented that address these issues for the high-level parallel language Orca. Communication and synchronization are done with ''shared data objects'', and the tool visualizes traces in relation to these objects. Orcshot possesses a powerful filter utility to achieve the necessary data reduction. Orcshot can be adapted to other object-based languages with slight effort. The orcshot performance visualization tool has already helped find numerous performance bugs. One example is presented.

关键词： parallel processing systems

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hardware implementation of windowing in a multicast packet switch

Hardware implementation of windowing in a multicast packet s...

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Proceedings of the 1996 IEEE 2nd International conference on algorithms & Architectures for parallel processing, ICA3PP

作者： Pinnu, Madhusudhana R. Sharma, Neeraj K. La Trobe Univ Melbourne

In a banyan based broadband packet switch using input queuing, the throughput of the switch is limited by the head of line blocking. Head of line blocking prevents packet in the input buffer from accessing an available output port in the network since the packet ahead of it in the buffer is blocked. Windowing is a technique used to mitigate the head of line blocking by relaxing the strict first-in-first-out queuing discipline of the input buffers. In this paper, we present a hardware implementation of windowing for a multicast packet switch. This implementation is further extended to include cyclic priority discipline to insure fairness among the input ports.

关键词： Packet switching

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Integrating synchronous and asynchronous paradigms: The Fork95 parallel programming language

Integrating synchronous and asynchronous paradigms: The Fork...

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Proceedings of the 1995 2nd International conference on Programming Models for Massively parallel Computers

作者： Kessler, Christoph W. Seidl, Helmut Universitaet Trier Trier Germany

The SB-PRAM is a lock-step-synchronous, massively parallel multiprocessor currently being built at Saarbruecken University, with up to 4096 RISC-style processing elements and with a (from the programmer's view) physically shared memory of up to 2 GByte with uniform memory access time. Fork95 is a redesign of the PRAM language FORK, based on ANSI C, with additional constructs to create parallel processes, hierarchically dividing processor groups into subgroups, managing shared and private address subspaces. Fork95 makes the assembly-level synchronicity of the underlying hardware available to the programmer at the language level. Nevertheless, it provides comfortable facilities for locally asynchronous computation where desired by the programmer. We show that Fork95 offers full expressibility for the implementation of practically relevant parallel algorithms. We do this by examining all known parallel programming paradigms used for the parallel solution of real-world problems, such as strictly synchronous execution, asynchronous processes, pipelining and systolic algorithms, parallel divide and conquer, parallel prefix computation, data parallelism, etc., and show how these parallel programming paradigms are supported by the Fork95 language and run time system.

关键词： parallel processing systems

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High Speed Pattern Matching in Genetic Data Base with Reconfigurable hardware

High Speed Pattern Matching in Genetic Data Base with Reconf...

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2nd International conference on Intelligent Systems for Molecular Biology, ISMB 1994

作者： Lemoine, Eric Quinqueton, Joel Sallantin, Jean Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier UMR 9928 Université Montpellier II/CNRS 161 rue ADA Cedex 5 Montpellier34392 France

ISBN: (纸本)0929280687

Homology detection in large data bases is probably the most time consuming operation in molecular genetic computing systems. Moreover, the progresses made all around the world concerning the mapping and sequencing of the genome of Homo Sapiens and other species have increased the size of data bases exponentially. Therefore even the best workstation would not be able to reach the scanning speed required. In order to answer this need we propose an algorithm, A2R2, and its implementation on a massively parallel system. Basically, two kinds of algorithms are used to search in molecular genetic data bases. The first kind is based on dynamic programming and the second on word processing, A2R2 belongs to the second kind. The structure of the motif (pattern) searched by A2R2 can support those from FAST, BLAST arid FLASH algorithms. After a short presentation of the reconfigurable hardware concept and technology used in our massively parallel accelerator we present the A2R2 implementation. This parallel implementation outperforms any kind of previously published genetic data base scanning hardware or algorithms. We report up to 25 million nucleotides per scanning seconds as our best results. © 1994, AAAI (***). All rights reserved.

关键词： Dynamic programming

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A methodology for evaluating parallel graph algorithms and its application to single source reachability 2

A methodology for evaluating parallel graph algorithms and i...

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2nd International conference on parallel and Distributed Information Systems, PDIS 1993

作者： Wolfson, Ouri Zhang, Weining Butani, Harish Kawaguchi, Akira Mok, Kui Department of Electrical Engineering and Computer Science University of Illinois ChicagoIL60680 United States Department of Mathematics and Computer Science University of Lethbridge LethbridgeAB3M4 Canada Department of Computer Science Columbia University New YorkNY10027 United States

ISBN: (纸本)0818633301

In this paper we consider parallel processing of a graph represented by a database relation, and we achieved two objectives. First, we propose a methodology for analyzing the speedup of a parallel processing strategy with the purpose of selecting at run-time one of several candidate strategies, depending on the hardware architecture and the input graph. Second, we study the single-source reachability problem, namely the problem of computing the set of nodes reachable from a given node in a directed graph. W e propose several parallel strategies for solving this problem, and we analyze their performance using our new methodology. The analysis is confirmed experimentally in a UNIX-Ethernet environment. © 1993 IEEE.

关键词： Directed graphs

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A parallel architecture for a VLSI-hardware-realization of a numerical stable variant of the Simplex-Method 2nd

A parallel architecture for a VLSI-hardware-realization of a...

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2nd Joint International conference on Vector and parallel processing, conpar 1992

作者： Schütz, Bernd Rauscher, Reinhard University of Hamburg Dept. of Computer Science Troplowitzstr. 7 Hamburg 542000 Germany

ISBN: (纸本)9783540558958

A hardware realization of the Simplex Method is represented. We customised the algorithm regarding numerical stability (arithmetics) and hardware proximity. The resulting hardware (VLSI custom chips, FPUs, RAM) of our accelerator is based on a parallel architecture with up to eight processing units. © Springer-Verlag Berlin Heidelberg 1992.

关键词： parallel architectures

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2nd Joint International conference on Vector and parallel processing, conpar 1992

2nd Joint International Conference on Vector and Parallel Pr...

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2nd Joint International conference on Vector and parallel processing, conpar 1992

ISBN: (纸本)9783540558958

The proceedings contain 130 papers. The special focus in this conference is on Vector and parallel processing. The topics include: Tolerating faults in synchronization networks;on incomplete hypercubes;reducing network hardware quantity by employing multi-processor cluster structure in distributed memory parallel processors;connection machine results for pyramid embedding algorithms;interconnection networks based on block designs;partitioning and mapping communication graphs on a modular reconfigurable parallel architecture;generalized shuffle-exchange networks;a mechanism for integrating a visualization tool with a symbolic debugger;the software-monitor DELTA-T and its use for performance measurements of some farming variants on the multi-transputer system damp;visualization of message passing parallel programs;parallel physical optimization algorithms for data mapping;profiling on a massively parallel computer;a multiprocessor multiwindow visualization subsystem;data race detection based on execution replay for parallel applications;the C_NET programming environment: an overview;P++, a C++ virtual shared grids based programming environment for architecture-independent development of structured grid applications;detection of concurrency-related errors in joyce;invariance properties in distributed systems;synchronization of parallel processes in distributed systems;statistical probabilistic clock synchronization algorithm;a SIMD architecture for medical imaging;computing the inner product on reconfigurable buses with shift switching;a novel sorting array processor;the time-parallel solution of parabolic partial differential equations using the frequency-filtering method;comparing the DAP, meiko and suprenum with a fluid dynamic benchmark and parallel detection algorithm of radar signals.

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