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International conference on Signals, Circuits and Systems, SCS

作者： Erik Hertz Peter Nilsson Department of Electrical and Information Technology Lund University Lund Sweden

This paper introduces a parabolic synthesis methodology for developing approximations of unary functions like trigonometric functions and logarithms which are specialized for efficient hardware mapped VLSI design. The advantages with the methodology are, short critical path, fast computation and high throughput enabled by a high degree of architectural parallelism. The feasibility of the methodology is shown by developing an approximation of the sine function for implementation in hardware.

关键词： hardware Application software Circuits and systems Circuit synthesis Signal synthesis Very large scale integration parallel processing Signal processing algorithms Table lookup Polynomials

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RESEARCH ON HIGH-SPEED MOTOR CONTROL BASED ON FPGA And SEMI-PHYSICAL SIMULATION

RESEARCH ON HIGH-SPEED MOTOR CONTROL BASED ON FPGA AND SEMI-...

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2024 CSAA/IET International conference on Aircraft Utility Systems, AUS 2024

作者： Wang, Xinyuan Sun, Lili Zhang, Run AVIC Shaanxi Aero Electric Co. Ltd No. 17 Jinye 2nd Road Xi’an China

With the advancement of more electric aircraft, the Environmental Control System (ECS) has progressively shifted from the traditional engine bleed mode to an electric drive mode. This transition not only significantly simplifies the aircraft's structure but also effectively reduces pollutant emissions. At the heart of the Electric ECS (EECS), the High-Speed Permanent Magnet Synchronous Motor (HSPMSM) stands out for its exceptional performance, with each rotation cycle requiring mere milliseconds or less. To ensure the stable operation of the HSPMSM at such high speeds, the design of its control system faces formidable challenges, particularly stringent requirements on control cycle times and latency. In response, this paper proposes an architecture integrating FPGA and DSP for precise HSPMSM control, aiming to significantly enhance the response speed of the control system. Within the control strategy for the HSPMSM, we innovatively incorporate advanced functional module designs such as the Coordinate Rotation Digital Computer (CORDIC) algorithm, Proportional-Integral (PI) controllers, and Space Vector Pulse Width Modulation (S VPWM) by using the powerful parallel processing capabilities of FPGA. Compared with traditional controllers like DSP for HSPMSM applications, the successful integration of FPGA with advanced control algorithms can effectively shorten the control cycle. Besides, by constructing a hardware-in-the-loop (HIL) real-time simulation model, we successfully demonstrated the remarkable advantages of the FPGA-based control system in terms of real-time performance, stability, and control accuracy. © The Institution of Engineering & Technology 2024.

关键词： hardware-in-the-loop simulation

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Implementation of FPGA-based hardware acceleration system for U-Net networks

Implementation of FPGA-based hardware acceleration system fo...

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Electrical Engineering, Big Data and algorithms (EEBDA), IEEE International conference on

作者： Peng Chen Liqiang Xu Wuhan University of Science and Technology Wuhan China

In recent years, with the rapid development of network technology in our country, neural network algorithm is widely recognized and applied to image. U-Net is one of them, which can effectively improve the efficiency of FPGA network hardware utilization, and thus enhance the acceleration system. The main principle of the U-Net is to accelerate the speed of convolutional computation by means of circular flow and circular unfolding, and to improve the performance of the network hardware. In order to learn more about it, this paper will discuss the relevant research.

关键词： Electrical engineering Constraint optimization Image recognition Neural networks parallel processing Big Data hardware acceleration

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A hardware Structure of HEVC Intra Prediction

A Hardware Structure of HEVC Intra Prediction

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International conference on Information Science and Control Engineering (ICISCE)

作者： Wei Lu Ningmei Yu Jianghan Nan Dongfang Wang Department of Electronics Engineering Xi'an University of Technology Xi'an China

ISBN: (纸本)9781467368513

In this paper a parallel hardware structure of ASIC for HEVC intra prediction encoding is proposed. This structure by analyzing software algorithm, according to the characteristics of the ASIC implementation of parallelization, designs the DC, a planar, horizontal and vertical Angle prediction hardware structure of the parallel processing, and finished the calculation of SATD. A parallel prediction hardware structure is designed in order to improve the computational efficiency. SATD calculated using a set of registers in the shift and 4-2 compression method implements the pipeline of processing, greatly improving the throughput rate and computational efficiency. After logic synthesis using the SMIC0.13μm standard cell library, simulation results show that the proposed architecture of 4×4 logic gates for 29.8K, on-chip cache to 6.8 KB. At 300MHz, real-time processing 3840×2160@25fps sequence of images, extremely suit for VLSI HD encoder.

关键词： Image coding hardware Registers Prediction algorithms Arrays Very large scale integration Encoding

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GPU-accelerated Principal-Agent Game for Scalable Citizen Science 19

GPU-accelerated Principal-Agent Game for Scalable Citizen Sc...

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2nd ACM SIGCAS conference on Computing and Sustainable Societies (COMPASS)

作者： Kabra, Anmol Xue, Yexiang Gomes, Carla P. Cornell Univ Dept Comp Sci Ithaca NY 14853 USA Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA

ISBN: (纸本)9781450367141

Citizen science programs have been instrumental in boosting sustainability projects, large-scale scientific discovery, and crowd-sourced experimentation. Nevertheless, these programs witness challenges in submissions' quality, such as sampling bias resulting from citizens' preferences to complete some tasks over others. The sampling bias frequently manifests itself in the program's dataset as spatially clustered submissions, which reduce the efficacy of the dataset for subsequent scientific studies. To address the spatial clustering problem, programs use reward schemes obtained from game-theoretical models to incentivize citizens to perform tasks that are more meaningful from a scientific point of view. Herein we propose a GPU-accelerated approach for the Avicaching game, which was recently introduced by the eBird citizen science program to incentivize birdwatchers to collect bird data from under-sampled locations. Avicaching is a Principal-Agent game, in which the principal corresponds to the citizen science program (eBird) and the agents to the birdwatchers or citizen scientists. Previous approaches for solving the Avicaching game used approximations based on mixed-integer programming and knapsack algorithms combined with learning algorithms, using standard CPU hardware. Following the recent advances in scalable deep learning and parallel computation on Graphical processing Units (GPUs), we propose a novel approach to solve the Avicaching game, which takes advantage of neural networks and parallelism for large-scale games. We demonstrate that our approach better captures agents' behavior, which allows better learning and more effective incentive distribution in a real-world bird observation dataset. Our approach also allows for massive speedups using GPUs. As Avicaching is representative of games that are aimed at reducing spatial clustering in citizen science programs, our scalable reformulation for Avicaching enables citizen science programs to tackle sampling b

关键词： Citizen Science Computational Sustainability Machine Learning Mixed-Integer Programming parallel Computation

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USA-JAPAN COMPUTER conference, 2nd, PROCEEDINGS, 1975.

AFIPS

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AFIPS 1975年

作者： Anon

One hundred and fourteen papers are presented on the following topics: pattern recognition and image processing;hardware system architecture;industrial applications;numerical methods and computations;hardware for processors, memory and peripherals;library automation;parallel processing;artificial intelligence and its applications;computers in health and medicine;computers in the instructional process;system performance and evaluation;banking and reservation systems;imaginative uses of computers;theoretical aspects of information processing;data bases and file management;specialized I/O;simulation and modeling;programming languages and translators;computer networks and data communications;computer graphics;data base security techniques;problem solving and programming methodology;economics of computer networks;automated design and debugging of hardware and software;and software techniques and algorithms. Selected papers are indexed separately.

关键词： Computers

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Image parallel processing Based on GPU

Image Parallel Processing Based on GPU

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The 2nd IEEE International conference on Advanced Computer Control(第二届先进计算机控制国际会议 ICACC 2010)

作者： Yun-shan Chen Nan Zhang Jian-li Wang Changchun Institute of Optics Fine Mechanics and Physics Chinese Academy of Sciences Graduate Scho Changchun Institute of Optics Fine Mechanics and Physics Chinese Academy of Sciences Changchun Chi

ISBN: (纸本)9781424458455;9781424458486;9781424458479;9781424458462

In order to solve the compute-intensive character of image processing, based on advantages of GPU parallel operation, parallel acceleration processing technique is proposed for image. First, efficient architecture of GPU is introduced that improves computational efficiency, comparing with CPU. Then, Sobel edge detector and homomorphic filtering, two representative image processing algorithms, are embedded into GPU to validate the technique. Finally, tested image data of different resolutions are used on CPU and GPU hardware platform to compare computational efficiency of GPU and CPU. Experimental results indicate tbat if data transfer time, between host memory and device memory, is taken into account, speed of the two algorithms implemented on GPU can be improved approximately 25 times and 49 times as fast as CPU, respectively, and GPU is practical for image processing.

关键词： Image processing parallel operation GPU CUDA

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A hybrid high-performance embedded processing System

A hybrid high-performance embedded Processing System

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International conference on Industrial Mechatronics and Automation, ICIMA

作者： Yi Deng Teng Long School of Information and Electronic Beijing Institute of Technology Beijing China

ISBN: (纸本)9781424476534

In this paper, we analyze the speedup formula, and expand the formula in detail. After discuss the timing problems of parallel computing, we give some designing rules, specially applied to HPEC (high-performance embedded computing) systems. Further analyzing the characteristics of HPEC system, a modular processing architecture is proposed. Due to the development of interconnection technologies, we design a type of hybrid PE (processing Element) architecture, and describe the compositions of the PE. The implementation methods of the hybrid PE are described. An actual platform is established to certify the feasibility and performance of the system.

关键词： Digital signal processing Computer architecture Field programmable gate arrays parallel processing Signal processing algorithms Industrial electronics Embedded computing Integrated circuit technology hardware Electronics industry

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High-Speed Data Transfer using AXI Protocol for Image Detection

High-Speed Data Transfer using AXI Protocol for Image Detect...

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Innovation in Technology (INOCON), IEEE International conference for

作者： Rajat Raj Sharat Kumar Miskin Naman Bhatia Electronics and Communication Engineering RV College of Engineering Bengaluru India

Convolutional neural networks (CNN) due to their excellent accuracy, have emerged as the leading machine learning method. However, it becomes difficult to deploy CNN algorithms on hardware platforms because of their high memory bandwidth, computational complexity, and power consumption. hardware accelerators such as Field Programmable Gate Arrays (FPGA), Graphics processing Unit (GPU), etc. are excellent platforms for modelling CNN algorithms. The purpose of the paper is to run a standard software process in hardware and exploit natural parallelism in hardware to speed up neural network prediction. The paper presents a rule-based synthesizable Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocol for high-speed data transmission. The paper develops a computer vision system on an FPGA that could recognize the numbers 0 through 9 written by hand for the capstone design project. The findings show that 91% accuracy is achieved through Rectified linear activation unit (ReLU) which can be increased to 98% by implementing the Sigmoid activation function with a depth of 10 bits. The method provides good accuracy and clock performance while using few resources.

关键词： Protocols Machine learning algorithms Computational modeling Software algorithms Neural networks Graphics processing units parallel processing

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Design of a processing element of a SIMD computer for genetic algorithms

Proceedings of the Conference on High Performance Computing ...

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Proceedings of the conference on High Performance Computing on the Information Superhighway, HPC Asia'97 1997年 688-691页

作者： Inoue, Tomio Sano, Masahiko Takahashi, Yoshizo Univ of Tokushima Tokushima Japan

We have been investigating the efficiency of Genetic algorithms (GA) for solving for a variety of real problems. During our investigations we have concluded that the large amount computational time required to find GA based solutions on conventional computers is restrictive. We are therefore developing an innovative new computer architecture, suitable for the solution of large scale problems using GAs. In this paper we introduce the SIMD-GA (Single Instruction stream Multiple Data stream Genetic Algorithm), and discuss its hardware design and implementation. By taking advantage of the recent advances is HDLs (hardware Description Language) and FPGA's (Field Programmable Gate Array) we have been able to quickly develop and prototype a PE (processing Element) for a SIMD-GA. This approach allows us to build a cost-effective parallel processing architecture to overcome the problem of the computational time required for traditional sequential GA implementation.

关键词： parallel processing systems

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