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AQuES: an agent-based query evaluation system

AQuES: an agent-based query evaluation system

引用

International conference on Cooperative Information Systems

作者： M. Stillger J.K. Obermaier J.C. Freytag Institut fur Informatk Humboldt-Universitaet zu Berlin Germany

Optimization for distributed and parallel database systems is an overly complex problem. This complexity arises due to the various kinds of parallelism and the coexistence of heterogeneous hardware modules. The query optimizers for those systems must exploit parallel algorithms for algebra operators, independent data parallelism and resource scheduling. In addition, unexpected deviations of the workload at runtime enforce new, dynamic execution strategies. This paper reports ongoing work in developing an agent-based query optimization and execution system to cope with this problem. It is based on the principles of distributed, symmetric processes which work in a cooperative, yet independent manner. This approach enables a dynamical adaptation to changes in the execution environment with local and simple actions. We present the architecture of the components and outline the principle of distributed query execution within this software system.

关键词： Query processing Database systems hardware Runtime parallel algorithms Power system modeling Distributed databases Job shop scheduling Computer architecture Software systems

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Towards smart-pixel-based implementation of wideband active sonar echolocation system for multi-target detection

Towards smart-pixel-based implementation of wideband active ...

引用

International conference on Signal processing and Communication Systems, ICSPCS

作者： Chien-Hsun Tseng Marina Cole School of Engineering University of Warwick UK

A modified adaptive noise cancelling (ANC) hybrid algorithm incorporating techniques of optimal wideband FIR filtering operation and the trimmed mean (TM)-levelization, a dynamic level-based thresholding process, is described in this paper for wideband active sonar echolocation system. This novel technique performs effective suppression of unwanted part of the training data thus localizing potentials of target returns. Furthermore, due to a massive parallelism in the system although the current electronic processing units such as GPU (graphic processing unit) and GPGPU (general-purpose GPU) work well, we propose the concept of smart-pixel (SP) as a possible solution towards hardware implementation of the above algorithm. In this architecture of parallelism, an array of optical devices is integrated onto one chip and then utilized as a computational cell to provide an alternative solution towards parallel implementation of the ANC hybrid algorithm.

关键词： Sonar detection Wideband Finite impulse response filter parallel processing Optical arrays Noise cancellation Filtering algorithms Adaptive filters Training data Graphics

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Implementation of a genetic algorithm based associative classifier system (ACS)

Implementation of a genetic algorithm based associative clas...

引用

International conference on Tools for Artificial Intelligence (ICTAI)

作者： K.E. Twardowski Syracuse University Syracuse NY USA

The first results from the development of a genetic algorithm-based ACS are presented. The ACS is a result of mapping the inherent parallelism in classifier systems to a program which executes on a PC-based associative processor. The associative algorithms of the ACS for the coherent processor are presented. It is demonstrated that this associative implementation of the BOOLE classifier system learns as well as results published for serial implementations. It is shown that the use of an associative processor as a co-processor can decrease classifier system response time, particularly for classifier systems with a large number of rules. In fact, when the number of rules in the ACS was increased by an order of magnitude, the response time of the system increased only 25% after DOS overhead was removed.< >

关键词： Genetic algorithms Computer aided manufacturing CADCAM hardware Real time systems Delay parallel processing Coprocessors Computer architecture Kirk field collapse effect

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Folded FFT architecture for real-valued signals based on Radix-23 algorithm

Folded FFT architecture for real-valued signals based on Rad...

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International conference on Devices, Circuits and Systems (ICDCS)

作者： Pradnya Zode Abhilesh Thor A. Y. Deshmukh Dept. of Electronics Engg. YCCE Nagpur India Deptt. Of Electronic Engg. GHRCE Nagpur India

A new FFT architecture for real-valued signal is proposed using Radix-2 3 algorithm. It is based on modifying flow graph of the FFT algorithm such that it has both real and complex datapaths. A redundant operation in flow graph is replaced by imaginary part. Using folding technique RFFT architecture with any level of parallelism can be achieved. This RFFT architecture will lead to low hardware complexity as compare to radix-2 and radix 22 algorithm in terms of adder, multiplier and delay. N-point 2 parallel radix-2 3 architecture requires (log 8 N-) complex multiplier, 2log 2 N adders, 3N/2-2 delays. RFFT which is used for real time applications and in portable devices for which low power consumption is main requirement, so accordingly carry propagate adder which has least power consumption and CSD multiplier is selected for our proposed architecture.

关键词： Computer architecture Adders Delays Signal processing algorithms Power demand hardware Flow graphs

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Optimized programmable hardware scheduler for reconfigurable MPSoCs

Optimized programmable hardware scheduler for reconfigurable...

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IEEE International conference on Green High Performance Computing (ICGHPC)

作者： P.M. Lalley T. Latha Department of Electronics and Communication Narayanaguru College of Engineering Manjalumoodu Marthandam India Department of Electronics and Communication St. Xavier's Catholic College of Engineering Chunkankadai Nagercoil India

Embedded System plays a vital role in consumer Industry. Complex applications need systems which contains multiple heterogeneous processors, running in parallel to speed up the system. Also due to area constraints, the processors are evolved in a single System on Chip called Multiprocessor System on Chip (MPSoC). The system should be reusable and debuggable, hence the designers designed and developed Reconfigurable MPSoCs rather than Application Specific Integrated Circuits (ASIC) in Field Programmable Gate Arrays (FPGA). Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However the growth of number of processing elements in one chip, task decomposition and scheduling become major bottlenecks of MPSoC architecture. To execute the applications, the application software is splitted as tasks and mapped to the different available processors and scheduled the tasks as when to execute in the available processors when the resources are ready. Selection of most suitable candidates for execution in a particular processor is very much important. hardware related tasks are executed in different hardware accelerators and software tasks in processors. The area occupied by the schedulers in memory is more in internal memory. For scheduling these tasks, a programmable hardware is developed as hardware scheduler in the reconfigurable MPSoC using NIOS II processor. The algorithm for optimized scheduling in the target architecture is proposed. The literature survey is made with the hardware scheduler and new target MPSoC architecture. Quartus II version 12.1 and SOPC Builder are used to configure the NIOS II processer. Nios II EDS software tool has been used to build the application code.

关键词： hardware Program processors Processor scheduling Computer architecture Software algorithms

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Recognition of access patterns for DSP kernel codes

Recognition of access patterns for DSP kernel codes

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International conference on Systems and Informatics (ICSAI)

作者： Xiaoyang Li Yu Liu Chen Gong Dake Liu Lab of Application Specific Instruction-set Processors Beijing Institute of Technology Beijing China

ISBN: (纸本)9781479954599

Kernel-stream programming is a state-of-the-art method to program on parallel Digital Signal processing (DSP) platforms. As the most legacy programs are written in sequential languages, a challenge of kernel-stream programming is to automatically recognize kernel code patterns and replace them with hardware optimized parallel library codes. In this paper, we try to solve an essential problem of kernel code recognition: the memory access patterns of matrix kernel codes. Though it is essential, most kernel recognizers previously did not recognize memory access patterns, simply recognizing only custom templates instead. We define eight 1-dimensional and 2-dimensional array access patterns frequently used in matrix kernel computing. The recognition algorithm is implemented in LLVM compiler infrastructure and is tested against several matrix kernels. Results show much improved matrix codes matches based on using our predefined access patterns. As modeling of access patterns in this paper is close to their original mathematical representations, limited number of kernel templates is needed to successfully complete recognitions of our interested matrix algorithms.

关键词： Decision support systems Lead conferences Informatics parallel programming Program processors Radio frequency

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Design and Analysis of Efficient On-Star Compression algorithms for FPGA Platforms

Design and Analysis of Efficient On-Star Compression Algorit...

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Computer, Vision and Intelligent Technology (ICCVIT), International conference on

作者： Guoliang Zhang Xueying Wang Jianpeng Fan College of Electronic Science and Technology National University of Defense Technology Changsha China

ISBN: (数字)9798331540043

ISBN: (纸本)9798331540050

Image compression has always been a hot topic in the field of aerospace. The onboard processing unit, due to its background of deep space operation, has greatly limited performance in terms of data storage and data transmission. Satellite remote sensing images are developing towards larger size, higher frame frequency, and more frequency bands, which increasingly demand storage space and processing power. There is an urgent need for a set of efficient and lightweight image compression hardware and software. Therefore, in this work, we have improved the Context-Based Adaptive Lossless Image Compression (CALIC) algorithm, including error quantization and entropy coding, to meet the requirements for on-orbit processing in terms of compression time and compression ratio. At the same time, aiming at the working scenario of on-orbit processing, we chose Field-Programmable Gate Array (FPGA) as the platform to deploy the improved CALIC and designed the arithmetic coding Av value calculation process in parallel on this basis, which greatly reduced the processing time on the hardware side. We have carried out simulation verification of this paper’s image compression algorithm on the KODAK24 and SZTAKI_Airchange datasets. The experimental results show that our method strikes a good balance between compression ratio and compression rate compared with typical compression algorithms, making it suitable for on-orbit processing scenarios.

关键词： Technological innovation Image coding Quantization (signal) Software algorithms hardware Software Field programmable gate arrays Remote sensing Compression algorithms Arithmetic

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Intelligent Microbial Growth Monitoring: A parallel OD600 Detection System Based on Artificial Intelligence

Intelligent Microbial Growth Monitoring: A Parallel OD600 De...

引用

Machine Vision, Image processing and Imaging Technology (MVIPIT), International conference on

作者： Libing Xu Fei Ren Bonifacio T. Doma Nanjing SuperKong Electronics Co. Ltd. China Nan Jing China School of Information Technology Mapua University Philippines School of Graduate Studies Mapua University Manila Philippines

ISBN: (数字)9798331543037

ISBN: (纸本)9798331543044

Microbial $\mathbf{OD}_{\mathbf{600}}$ measurement is a crucial experimental technique in microbiological and molecular biological research, evaluating microbial growth by measuring optical density at 600 nm wavelength. While convenient, this method has limitations. For instance, different microbial species and growth stages may absorb light differently, potentially leading to biases when measuring multiple strains simultaneously. This paper presents an innovative parallel $\mathbf{OD}_{\mathbf{600}}$ detection system capable of simultaneously monitoring growth curves of multiple microbial strains. Our research integrates advanced optical systems, precise mechanical control, and artificial intelligence algorithms, not only improving the accuracy and efficiency of bacterial growth measurements but also achieving parallel processing and analysis of multiple samples. We discuss in detail the hardware design, software architecture, and core algorithms, with particular emphasis on the application of machine learning in multi-strain data analysis and prediction. Experimental results demonstrate that this system significantly outperforms traditional methods in measurement accuracy, automation level, multi-sample processing capability, and data analysis.

关键词： Temperature measurement Accuracy Current measurement Wavelength measurement Machine learning Optical variables measurement Prediction algorithms Real-time systems Monitoring Strain

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parallel Computation strategies for Fractal Compression

Parallel Computation strategies for Fractal Compression

引用

International conference on Advances in Computing, Communication Control and Networking (ICACCCN)

作者： Bejoy Varghese Krishnakumar S. Federal Institute of Science And Technology Angmaly Kerala India School of Technology and Applied Sciences Kochi Kerala India

ISBN: (数字)9781728183374

ISBN: (纸本)9781728183381

Fractal coding is a lossy compression scheme and had an extra edge in the early 90s because of its ability to consider the self-similarities in an image. But the high computational cost involved in its encoding process made it impractical for commercial applications. This is due to the hard task of calculating various affine transformations in the comparison of range and domain pools. But the advantages in using FIC algorithms are less complex decoding process, high PSNR, better SSIM, dimensionless scheme and high compression ratio. Recent improvements in the computing techniques put back the FIC on track by reducing the computational cost involved in the encoding process. This paper suggests the importance and use of parallel computation techniques such as General Purpose Graphical processing Unit (GPGPU) and Compute Unified Device Architecture (CUDA) in Fractal based image compression algorithms. Analysis of the empirical results shows that the parallel computational approaches could significantly reduce the encoding time as the calculation of fractal affine transformations (AT) can be largely parallelized.

关键词： Image coding Graphics processing units Machine learning Fractals hardware Computational efficiency Task analysis

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Towards a smart selection of resources for low-energy multimedia processing

Towards a smart selection of resources for low-energy multim...

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International conference on Cloud Technologies and Applications (CloudTech)

作者： Sidi Ahmed Mahmoudi Faculty of Engineering University of Mons Belgium

ISBN: (纸本)9781467388955

Today, one can find images and videos everywhere, they can come from cameras, mobile phones or from other devices. These images and videos are used to illustrate different objects in a large number of situations (airports, hospitals, public areas, sport events, etc.). This makes the task of processing images and videos a necessary tool that can be used for various domains related to computer vision. The performance of these algorithms have been so reduced due to their high intensive computation and energy consumption. In this work, we propose a new framework that allows users to select in a smart and efficient way the computing units (CPU or/and GPU) in case of processing single image, multiple images, multiple videos or single video in real time. This framework enables to affect the CPU or/and GPU units for calculation depending on the type of media to process and the algorithm complexity. The framework provides several image and video functions on GPU, such as silhouette extraction, points of interest extraction, edges detection, sparse and dense optical flow estimation. These functions are exploited in different applications such as vertebra segmentation in X-ray and MR images, gaze estimation, event detection and localization in real time. Experimental results have been obtained by applying the framework for different use case applications showing a speedup ranging from 5 to 116×, by comparison with sequential CPU implementations. In addition to these performance, the parallel and heterogeneous implementation offered lower power consumption as a result for the fast treatment.

关键词： Biomedical imaging Performance evaluation Estimation Cameras Image edge detection hardware Graphics processing units

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