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检索条件"任意字段=2nd IEEE Symposium on Parallel and Distributed Processing, SPDP 1990"

共 165 条记录，以下是61-70 订阅

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The European Declarative System (EDS) as a platform for parallel logic programming 2

The European Declarative System (EDS) as a platform for para...

引用

2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Wong, K.-F. Baron, U.C. Benker, H. Bescos, S. Cheese, A.B. Cosquer, F.J.N. Delgado-Rannauro, S.A. Dorochevsky, M. Heuze, P. Ibanez-Espiga, M. Noye, J. Paci, M. Ratcliffe, M.J. Reeve, M.J. Schuerman, K. Sexton, A. Veron, A. Xu, J. Computer Architecture Group Arabcllastrasse 17 Munich 81D8000 Germany

ISBN: (纸本)0818620870

关键词： Logic programming

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Self-testing and self-reconfiguration architecture for 2-D WSI arrays 2

Self-testing and self-reconfiguration architecture for 2-D W...

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2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Abujbara, Hussatn Y. Al-Arian, Sami A. Computer Science and Engineering Department University of South Florida TampaFL33620 United States

ISBN: (纸本)0818620870

A self-testing and self-reconfiguration method for both production and field repair for a 2-D wafer scale integration (WSI) array is presented. A distributed built-in-self-test (BIST) tests all processing elements (PEs) of the wafer simultaneously. While some techniques use local BIST at each individual PE, such BIST cannot test the interconnection network. A global bypass-through bus is used to communicate data simultaneously to all PEs. Multiple input shift registers (MISRs) for random test generation are used where only 2m MISRs are needed for m m array of PEs. In this design, the overhead consists of two simple multiplexers, two registers, a simple maintenance control logic and a comparator for each PE. A guided ripple replacement (GRR) reconfiguration technique is used with a maximum interconnection edge of 2D length, where D is the diagonal distance in the largest area of clustered defected PEs. This upper limit length is optimal. The algorithm is capable of dealing with heavily clustered defects. The approach optimizes the area overhead and performance, by sharing the control network to perform reconfiguration after testing the PEs. The array structure can be flexibly designed to accommodate different reconfiguration techniques without significant modification. © 1990 ieee.

关键词： Shift registers

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A strict monolithic array constructor 2

A strict monolithic array constructor

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2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Gao, Guang R. Yates, Robert Kim Dennis, Jack B. Mullin, Lenore M. R. School of Computer Science McGill University 3480 University St. MontrealPQH3A 2A7 Canada Laboratory for Computer Science Massachusetts Institute of Technology 545 Technology Square CambridgeMA02139 United States Dept. of Comp. Sci. and Elec. Eng. University of Vermont BurlingtonVT05405 United States

ISBN: (纸本)0818620870

Despite their importance in scientific computation, arrays have posed a serious persistent challenge to the efficient implementation of functional languages. We propose a new monolithic array constructor which provides a solution to two major problems arising in the implementation of mono-lithic arrays: (1) the overhead of scheduling and synchronization for recursively defined arrays;(2) the copying of the intermediate arrays during array construction. Our array constructor allows an index domain to be constructed from a set of rectangular index regions and combinations of these. An or-dered sequence of regions may be specified in a fashion which can be checked a compiler using simple subscript analysis techniques. An array is also allowed to be monotonically defined by iteration without using incremental array update operations. © 1990 ieee.

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parallel algorithms for determining k-width- connectivity in binary images 2

Parallel algorithms for determining k-width- connectivity in...

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2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Dehnc, Frank Hambrusch, Susanne E. School of Computer Science Carleton University OttawaK1S 5B6 Canada Department of Computer Sciences Purdue University West LafayetteIN47907 United States

ISBN: (纸本)0818620870

In this paper we consider a new form of connectivity in binary images, called k-width-connectivity. Two pixels a and 6 of value are in the same k-width- component if and only if there exists a path of width k such that a is one of the k start pixels and b is one of the k end pixels of this path. We present characterizations of the k-width-components and show how to determine the k-width-components of an n x n image in O(n) and 0(log2 n) time on a mesh of processors and hypercube, respectively, when the image is stored with one pixel per processor. Our methods use a reduction of the k-width-connectivity problem to the 1-width-connectivity problem. A distributed, space-efficient encoding of the k-width-components of small size allows us represent the solution using O(l) registers per processor. Our hypercube algorithm also implies an algorithm for the shuffle-exchange network. © 1990 ieee.

关键词： Pixels

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Synthesis of simple distributed detection networks 2

Synthesis of simple distributed detection networks

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2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Rao, Nageswara S.V. Department of Computer Science Old Dominion University NorfolkVA23529-0162 United States

ISBN: (纸本)0818620870

We studies algorithmic issues of simple object detection problems in the context of a system consisting of a finite set of sensors S that monitor a workspace. Each sensor a in S detects the presence of any object that belongs to a certain subset, Det(a), of a given set of objects O. The detection problem is defined as follows: given that an object had been detected at a subset D contained in S of sensors, identify if the object in the workspace could be a member of O. If yes, compute the maximal set of such members. If not, declare the object in the workspace to be unidentified. Two versions are considered of this problem based on how the input is specified. In the forward detection problem, one is given (Det(a))/sub a in S/. In the backward detection problem, one is given (Set(b))/sub b in O/, where Set(b) is the set of sensors at which the object b in O would be detected. The article constructs a conceptual graph structure called the detection network that yields efficient implementation of detection algorithms using combinational circuits, message-based systems and parallel computing systems. It shows the problem of computing a network with minimum number of edges is computationally intractable, and then presents several polynomial-time approximation algorithms. Then it presents sequential algorithms to solve the detection problems with and without preprocessing. It also discusses parallel algorithms on shared memory systems and hypercube-based message passing systems. Finally, it shows that the problem of recognizing multiple objects is computationally intractable. © 1990 ieee.

关键词： Object detection

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Forward chaining parallel inference1 2

Forward chaining parallel inference1

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2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Rowe, Michael C. Labhart, Jay Bechtel, Robert Matney, Steve Carrow, Steve Merit Technology Incorporated 5068 W. Plano Parkway PlanoTX75093-5009 United States Naval Research Laboratory 4555 Overlook Ave. S.W. WashingtonD.C.20375-5000 United States

ISBN: (纸本)0818620870

Rule based inference has demonstrated its applicability in a wide variety of domains. As the scope of these systems has increased, the execution speed has become unacceptable. One method of improving inference performance is parallelization. The parallelization of inference is not as straight-forward as the parallelization of traditional numeric algorithms. This paper describes the completed and ongoing efforts of the parallel Inferencing Performance Evaluation and Refinement project1 (PIPER). The PIPER inference engine is based on the Merit Enhanced Traversal Engine (METE) algorithm which is an extension of Forgy's (1979) RETE algorithm. To evaluate the efficacy of this design and implementation, an iterating 108 rule knowledge base was composed. This rule set was designed to roughly simulate the information rich nature of its target application domain, Strategic Defense Initiative contact discrimination, and was processed on from 7 to 89 Butterfly Plus processor nodes. Three uniprocessor control groups were also employed to gauge speed-up. Using the control group which produced the most conservative speed-up factors, the Phase I inference engine achieved a maximum true speed-up in excess of 31 utilizing 45 processors. This speed-up was attributed to: parallelism in constant and two input node tests, pipelining between: Two input node tests and conflict resolution, test processing and overhead corresponding to the parallel implementation. © 1990 ieee.

关键词： Inference engines

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Modeling the retinal horizontal cell layer on a massively parallel processor: A detailed neural network model 2

Modeling the retinal horizontal cell layer on a massively pa...

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2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Kimball, Anthony L. Winslow, Raimond L. Army High Performance Computing Research Center United States Departments of Computer Science United States Physiology University of Minnesota MinneapolisMN55455 United States

ISBN: (纸本)0818620870

We describe the use of a massively parallel processor , the Connection Machine model CM-2, to simulate light responses of the horizontal cell network of the vertebrate outer retina. The network model is biophysically detailed;properties of all non-linear voltage-gated membrane currents and intracellular calcium buffering mechanisms are modeled. Implementation and efficiency of execution on CM-2 and Cray supercomputers is discussed. Computational properties of the horizontal cell network under light and dark adapted conditions are analyzed. Results demonstrate that an increase in cell coupling following light adaptation improves the temporal resolution of the network at the expense of decreased spatial resolution. These changes may perform matched filtering, adjusting the response kinetics of the horizontal cell network to match those of cone photoreceptors over a range of background light levels. © 1990 ieee.

关键词： Cytology

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Efficient parallel algorithms for solving set recurrence equations and applications 2

Efficient parallel algorithms for solving set recurrence equ...

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2nd ieee symposium on parallel and distributed processing, spdp 1990

作者： Ibarra, Oscar H. Wang, Hui Jiang, Too Department of Computer Science University of California Santa BarbaraCA93106 United States Department of Computer Sciences and Systems McMaster University HamiltonONL8S 4K1 Canada

ISBN: (纸本)0818620870

The authors present two EREW PRAM algorithms and one CREW PRAM algorithm for solving set recurrence equations of the type commonly used in dynamic programming solutions to many problems in pattern matching, sequence comparison, and language recognition. All three algorithms run in O(log2n) time. The first EREW PRAM algorithm uses O(M(n/log n)log2n) processors, where M(n) is the number of processors needed to multiply two n n Boolean matrices in O(log n) time on an EREW PRAM. The second algorithm uses O(M'(n/(log n square root loglog n))log2n) processors, where M'(n) is the number of processors needed to multiply two n n matrices over an arbitrary ring in O(log n) time on an EREW PRAM. The CREW PRAM algorithm uses O(M»(n/log/sup 1.5/n)log2n) processors, where M»(n) is the number of processors needed to multiply two n n matrices over an arbitrary ring in O(log n) time on a CREW PRAM. The authors show that linear context-free languages can be recognized in O(log2n) time using o(M(n)) processors on an EREW PRAM. They give applications to other problems such as string shuffling, recognition of languages accepted by two-head nondeterministic finite automata, and transductions defined by two-tape nondeterministic finite transducers. © 1990 ieee.

关键词： Pattern matching

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CASS 2012: The 2nd Workshop on Communication Architecture for Scalable Systems

CASS 2012: The 2nd Workshop on Communication Architecture fo...

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26th ieee International parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Flich, Jose Pakin, Scott Stunkel, Craig Univ Politecn Valencia Valencia Spain Los Alamos Natl Lab Los Alamos NM USA IBM Res Armonk NY 10504 USA

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2nd workshop on personal computer based networks of workstations (PC-NOW’99) 13th

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13th International parallel processing symposium, IPPS 1999 Held in Conjunction with the 10th symposium on parallel and distributed processing, spdp 1999

ISBN: (纸本)3540658319

Clusters composed of fast personal computers are becoming more and more attractive as cheap and efficient platforms for distributed and parallel applications. The main drawback of a standard NOWs is the poor performance of the standard inter-process communication mechanisms based on RPC, sockets, TCP/IP, Ethernet. Such standard communication mechanisms perform poorly both in terms of throughput as well as message latency. Recently, several prototypes developed around the world have proved that re-visiting the implementation of the communication layer of a standard Operating System kernel, a low cost hardware platform composed of only commodity components can scale up to several tens of processing nodes and deliver communication and computation performance exceeding the one delivered by the conventional high-cost parallel platforms. This workshop provides a forum to discuss issues related to the design of efficient NOWs based on commodity hardware and public domain operating systems as compared to custom hardware devices and/or proprietary operating systems. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Personal computers

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