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检索条件"任意字段=2nd International Conference on Hardware/Software Codesign and Systems Synthesis"
157 条 记 录,以下是1-10 订阅
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hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
Hardware synthesis from coarse-grained dataflow specificatio...
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2nd international conference on hardware/software codesign and systems synthesis
作者: Jung, H Ha, S Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume... 详细信息
来源: 评论
Current flattening in software and hardware for security applications
Current flattening in software and hardware for security app...
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2nd international conference on hardware/software codesign and systems synthesis
作者: Muresan, R Gebotys, C Univ Guelph Guelph ON N1G 2W1 Canada
This paper presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation de... 详细信息
来源: 评论
RTOS-centric hardware/software cosimulator for embedded system design
RTOS-centric hardware/software cosimulator for embedded syst...
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2nd international conference on hardware/software codesign and systems synthesis
作者: Honda, S Wakabayashi, T Tomiyama, H Takada, H Toyohashi Univ Technol Dept Informat & Comp Sci Toyohashi Aichi 4418580 Japan
This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model o... 详细信息
来源: 评论
System-level power-performance tradeoffs for reconfigurable computing
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年 第7期14卷 730-739页
作者: Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain
In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-... 详细信息
来源: 评论
hardware/software codesign for Portable Optical Coherence Tomography (OCT) Applications  7
Hardware/Software Codesign for Portable Optical Coherence To...
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Joint 7th international conference on Informatics, Electronics & Vision (ICIEV) / 2nd international conference on Imaging, Vision and Pattern Recognition (icIVPR)
作者: Tang, Song-Nien Hsiang, Chih-Yu Huang, Sheng-Jie Chung Yuan Christian Univ Dept Informat & Comp Engn Taoyuan Taiwan
This paper presents a hardware-software codesign scheme for the image formation of the Fourier-domain optical coherence tomography (FDOCT) system. Using a hardware processor, the fast Fourier transform (FFT) together ... 详细信息
来源: 评论
Memory accesses management during high level synthesis
Memory accesses management during high level synthesis
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2nd international conference on hardware/software codesign and systems synthesis
作者: Corre, G Senn, E Bomel, P Julien, N Martin, E Univ S Brittany LESTER F-56321 Lorient France
We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory ... 详细信息
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ASAP: an asynchronous array processor for hardware-software coprocessing and codesign
ASAP: an asynchronous array processor for hardware-software ...
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Proceedings of the 1996 2nd international conference on ASIC
作者: Gao, Bo Rees, David J. Univ of Newcastle upon Tyne Newcastle upon Tyne United Kingdom
Traditional field programmable gate arrays (FPGAs) originate and are used to prototype digital designs. Recently, there has been increasing interest in using FPGAs as attached systems for hardware-software coprocessin... 详细信息
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CoChrono: A Unified hardware/software Performance Analysis Tool for SoC-FPGA codesign  22
CoChrono: A Unified Hardware/Software Performance Analysis T...
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22nd IEEE Interregional NEWCAS conference (NEWCAS)
作者: Portas, Fabien Bois, Guy Savaria, Yvon Polytech Montreal Comp Engn Dept Montreal PQ Canada Polytech Montreal Elect Engn Dept Montreal PQ Canada
High-level embedded system design tools are making the design of complex SoC-FPGA systems more accessible than ever before. However, this comes at the cost of more opacity as implementations result from heavy transfor... 详细信息
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A Li-Ion cell testbench for fast Characterization and modeling
A Li-Ion cell testbench for fast Characterization and modeli...
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2nd international conference on Control, Decision and Information Technologies (CoDIT)
作者: Cicero, L. Tanougast, C. Ramenah, H. Sieler, L. Lecerf, F. Univ Lorraine LCOMS ASEC Team F-57070 Metz France
To develop efficient Li-ion powered systems, Cell testing and charactering are required to evaluate cell performance. However, testbenches are really expensive and test procedures provided are not the ones expected. I... 详细信息
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Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking
Reducing power and latency in 2-D mesh NoCs using globally p...
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2nd international conference on hardware/software codesign and systems synthesis
作者: Nilsson, E Öberg, J Royal Inst Technol Lab Elect & Comp Syst LECS IMITKTH Electrum SE-16440 Kista Sweden
One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem has been proposed over the years. For Networks-on-Chip... 详细信息
来源: 评论