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2nd international conference on hardware/software codesign and systems synthesis

作者： Jung, H Ha, S Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea

ISBN: (纸本)1581139373

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

关键词： HW/SW codesign system level design dataflow graph(DFG) VHDL autonomic hardware synthesis

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Current flattening in software and hardware for security applications

Current flattening in software and hardware for security app...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Muresan, R Gebotys, C Univ Guelph Guelph ON N1G 2W1 Canada

ISBN: (纸本)1581139373

This paper presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, a new real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.

关键词： current flattening power analysis attacks hardware architecture

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RTOS-centric hardware/software cosimulator for embedded system design

RTOS-centric hardware/software cosimulator for embedded syst...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Honda, S Wakabayashi, T Tomiyama, H Takada, H Toyohashi Univ Technol Dept Informat & Comp Sci Toyohashi Aichi 4418580 Japan

ISBN: (纸本)1581139373

This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

关键词： RTOS cosimulation embedded systems

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System-level power-performance tradeoffs for reconfigurable computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年第7期14卷 730-739页

作者： Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology hag been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology, and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： hardware/software (HW/SW) codesign power-performance tradeoffs reconfigurable computing (RC)

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hardware/software codesign for Portable Optical Coherence Tomography (OCT) Applications 7

Hardware/Software Codesign for Portable Optical Coherence To...

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Joint 7th international conference on Informatics, Electronics & Vision (ICIEV) / 2nd international conference on Imaging, Vision and Pattern Recognition (icIVPR)

作者： Tang, Song-Nien Hsiang, Chih-Yu Huang, Sheng-Jie Chung Yuan Christian Univ Dept Informat & Comp Engn Taoyuan Taiwan

ISBN: (纸本)9781538651636

This paper presents a hardware-software codesign scheme for the image formation of the Fourier-domain optical coherence tomography (FDOCT) system. Using a hardware processor, the fast Fourier transform (FFT) together with its front-end DC noise removal and re-sampling operations can be efficiently performed. In cooperation with the hardware unit, a software platform can properly execute the flexible magnitude compression and dynamic range mapping which are associated with the OCT image display. Moreover, the calibration process can also be performed using the same software platform. The proposed design could be developed based on a small-scale system, which lends support to the trend of portable FDOCT applications. System-level design verification was performed using an FPGA module and a mobile phone to evaluate the efficacy of the proposed hardware/software codesign scheme. By accessing the raw data through a pattern generator, the 16.2-fps OCT image display (in the 1024x1000 resolution) can be achieved in the developed FPGA-phone verification system.

关键词： optical coherence tomography OCT Fourier-domai FDOCT hardware/software codesign

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Memory accesses management during high level synthesis

Memory accesses management during high level synthesis

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2nd international conference on hardware/software codesign and systems synthesis

作者： Corre, G Senn, E Bomel, P Julien, N Martin, E Univ S Brittany LESTER F-56321 Lorient France

ISBN: (纸本)1581139373

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

关键词： memory aware behavioral synthesis

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ASAP: an asynchronous array processor for hardware-software coprocessing and codesign

ASAP: an asynchronous array processor for hardware-software ...

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Proceedings of the 1996 2nd international conference on ASIC

作者： Gao, Bo Rees, David J. Univ of Newcastle upon Tyne Newcastle upon Tyne United Kingdom

Traditional field programmable gate arrays (FPGAs) originate and are used to prototype digital designs. Recently, there has been increasing interest in using FPGAs as attached systems for hardware-software coprocessing and codesign. However, existing FPGAs on the market all implement general purpose logic designs. They are not well defined for the coprocessing and codesign purpose. In this paper, an analysis and comparison of existing FPGA architectures against requirements from synthesis process on algorithm specifications is described. Based on this analysis, the design of a configurable ASynchronous Array Processor (ASAP) and the development of a data-driven multiple thread computation model for the processor are presented. The system's performance is data dependent and measured by average instead of worst cases in synchronous FPGAs. The ASAP easily out-performs other coprocessing systems as a frame buffer by embedding a fast forward difference polynomial evaluation algorithm.

关键词： Parallel processing systems

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CoChrono: A Unified hardware/software Performance Analysis Tool for SoC-FPGA codesign 22

CoChrono: A Unified Hardware/Software Performance Analysis T...

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22nd IEEE Interregional NEWCAS conference (NEWCAS)

作者： Portas, Fabien Bois, Guy Savaria, Yvon Polytech Montreal Comp Engn Dept Montreal PQ Canada Polytech Montreal Elect Engn Dept Montreal PQ Canada

ISBN: (纸本)9798350361766;9798350361759

High-level embedded system design tools are making the design of complex SoC-FPGA systems more accessible than ever before. However, this comes at the cost of more opacity as implementations result from heavy transformations made by high-level synthesis tools, while there is a lack of complete suitable performance analysis tools for the resulting implementations. This paper proposes a unified application programmer interface and methodology that enables the extraction of time points to instrument performance metrics for hardware/software co-simulation and monitoring the SoC-FPGA execution. The proposed tool, called CoChrono, leverages high-level synthesis and code generation to access metrics similarly in software and hardware C++ code. The tool's features and low overhead are demonstrated with a practical application of architecture exploration and simulation model validation. Compared to instruments manually inserted using existing tools, CoChrono significantly reduces the effort required to validate complex timing constraints in hardware/software systems.

关键词： monitoring instrumentation SoC-FPGA HLS performance metrics HW/SW codesign system-level design

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A Li-Ion cell testbench for fast Characterization and modeling

A Li-Ion cell testbench for fast Characterization and modeli...

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2nd international conference on Control, Decision and Information Technologies (CoDIT)

作者： Cicero, L. Tanougast, C. Ramenah, H. Sieler, L. Lecerf, F. Univ Lorraine LCOMS ASEC Team F-57070 Metz France

ISBN: (纸本)9781479967735

To develop efficient Li-ion powered systems, Cell testing and charactering are required to evaluate cell performance. However, testbenches are really expensive and test procedures provided are not the ones expected. In this article, we propose a testbench design based on Instrumentation software and hardware co-design. An efficient charging and discharging hardware has been proposed and developed by using a remotable laboratory supply as main virtual component. software mechanisms are explained where the test procedures are detailed. in a second part. Acquisition constraints for measuring equipment are also specified in order to obtain relevant and valid data.

关键词： hardware-software codesign power engineering computing secondary cells discharging hardware instrumentation software-hardware codesign lithium-ion cell testbench lithium-ion powered systems remotable laboratory supply software mechanisms testbench design virtual component Batteries Computer architecture hardware Instruments Power supplies software Temperature measurement virtual component Batteries Power engineering computing Secondary batteries hardware/software co-design Electric Power Source Computer Architecture Computer hardware temperature measurement computer software Testing Procedures lithium ion battery

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Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking

Reducing power and latency in 2-D mesh NoCs using globally p...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Nilsson, E Öberg, J Royal Inst Technol Lab Elect & Comp Syst LECS IMITKTH Electrum SE-16440 Kista Sweden

ISBN: (纸本)1581139373

One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem has been proposed over the years. For Networks-on-Chip (NoC), where computational Resources are organised in a 2-D mesh connected together through Switches in an on-chip interconnection network, another possibility exists: Globally Pseudochronous Locally Synchronous clock distribution. In this paper, we present a clocking scheme for NoCs that we call Globally Pseudochronous Locally Synchronous, in which we distribute a clock with a constant phase difference between he switches. As a consequence of the phase difference, some paths along the NoC switch network become faster than the others. We call these paths Data Motorways. By adapting the switching policy in the switches to prefer data to use the motorways, we show that the latency within the network is reduced with up to 40% compared to a synchronous reference case. The phase difference between the resources also makes the circuit more tolerant to clock skew. It also distributes the current peaks more evenly across the clock period, which lead to a reduction in peak power, which in turn further reduces the clock skew and the jitter in the clock network.

关键词： clocking GALS GPLS mesh network on chip pseudochronous hot-potato

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