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CASES 2001 - Proceedings of the 2001 international conference on Compilers, Architecture, and synthesis for Embedded systems

CASES 2001 - Proceedings of the 2001 International Conferenc...

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2nd international conference on Compilers, Architecture, and synthesis for Embedded systems, CASES 2001

ISBN: (纸本)1581133995

The proceedings contain 31 papers. The topics discussed include: design space characterization for architecture/compiler co-exploration;storage allocation for embedded processors;an empirical evaluation of high level transformations for embedded processors;a novel approach to code analysis of digital signal processing systems;the very portable optimizer for digital signal processors;patchable instruction ROM architecture;hardware compilation of sequential Ada;a new method for compiling schizophrenic synchronous programs;transparent data-memory organizations for digital signal processors;a vision for embedded software;combined partitioning and data padding for scheduling multiple loop nests;heterogeneous memory management for embedded systems;establishing a tight bound on task interference in embedded system instruction caches;personal, handheld, wireless: the future of digital technology;pattern matching in reconfigurable logic for packet classification;personal, handheld, wireless: the future of digital technology;efficient longest executable path search for programs with complex flows and pipeline effects;and tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.

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Automatic performance model synthesis from hardware verification models 11

Automatic performance model synthesis from hardware verifica...

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Proceedings of the 2nd ACM/SPEC international conference on Performance engineering

作者： Bell Jr., Robert H. Sustik, Matyas Cummings, David W. Jackson, Jonathan R. IBM Systems and Technology Group Austin TX United States

ISBN: (纸本)9781450305198

Performance models are typically written by hand for a new model or assembled piece-meal from the prior simulation code of an old model. In either case, many man-months of work may be required to write the new model and validate design details against a prior or current design. In reality, the majority of information about the performance of the design already exists in the design structure of either the old hardware model or the new model or both. To harvest this information and eliminate the significant duplicate coding and validation efforts, we propose that a performance model be automatically synthesized from a prior or current hardware design using a bottom-up, design-oriented approach. We demarcate the performance-critical boundaries of the design and perform backward-trace cone analysis to identify logic to include in the performance model. We then abstract specific components for design changes and expend modeling effort only on the few functions relevant to a particular design study. Engineering effort then becomes focused on workload selection and quality, defining and projecting new designs, and assessing design tradeoffs and sensitivities - the small set of tasks with the highest potential to improve design performance. We present a case-study that shows that even the simplest proposed transformations on a high-performance IBM L2 cache design result in a simulation speedup of 3.9, with evidence that an order of magnitude speedup can be obtained using a few additional modeling abstractions.

关键词： Benchmarking

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6th international Workshop on Field-Programmable Logic and Applications, FPL 1996

6th International Workshop on Field-Programmable Logic and A...

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6th international Workshop on Field-Programmable Logic and Applications, FPL 1996

ISBN: (纸本)9783540617303

The proceedings contain 50 papers. The special focus in this conference is on High-level Design I, New software and hardware Development Tools. The topics include: Portable pipeline synthesis for FCCMs;a framework for developing parametrised FPGA libraries;co-evaluation environment for FPGA architecture and CAD system;an universal CLA adder generator for SRAM-based FPGAs;a data driven computer on a virtual hardware;custom computing machines vs. hardware/software codesign;reconfigurable and adaptive computing environment;computing 2-D DFTs using FPGAs;computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping;architectural synthesis and efficient circuit implementation for field programmable gate arrays;reconfigurable pipelined datapath;solving satisfiability problems on FPGAs;FPGA implementation of the block-matching algorithm for motion estimation in image coding;parallel CRC computation in FPGAs;coherent demodulation with FPGAs;the trianus system and its application to custom computing;flexible codesign target architecture for early prototyping of CMIST systems;a reconfigurable multiprocessor testbed;a slow motion engine for the analysis of FPGA-based prototypes;implementing reconfigurable datapaths in FPGAs for adaptive filter design;a fast constant coefficient multiplier for the XC6200;key issues for user acceptance of FPGA design tools;reconfigurable DSP demonstrators for the development of spacecraft payload processors;reconfigurable logic based fibre channel network card with sub 2 micro-second raw latency;an instruction-level custom-configurable processor;architectural synthesis techniques for dynamically reconfigurable logic and fast reconfigurable crossbar switching in FPGAs.

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An Optimized and Unified Architecture Design for H.265/HEVC 1-D Inverse Core Transform 2

An Optimized and Unified Architecture Design for H.265/HEVC ...

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2nd international conference on Image Processing, Applications and systems (IPAS)

作者： Kammoun, Ahmed Belghith, Fatma Loukil, Hassen Masmoudi, Nouri Univ Sfax Sfax Natl Sch Engn Elect & Informat Technol Lab Sfax Tunisia

ISBN: (纸本)9781509016457

This work proposes an FPGA architecture for the 1-D inverse transform of the latest video coding standard called the High Efficiency Video Coding standard (HEVC). This paper presents a new technique which computes the different sizes of the transform unit using a flexible architecture. Based on symmetrical characteristics of the elements in inverse transform matrices, the transform matrix is factorized into several matrices. This architecture supports all transform sizes i.e. 4x4, 8x8, 16x16, and 32x32. The synthesis results contributed to an operational frequency of up to 284 MHz (Altera Quartus II software) which is sufficient to encode high resolution videos in real-time.

关键词： High Efficiency Video Coding (HEVC)-Fast Algorithm-Inverse Core Transform-Optimized hardware Implementation

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hardware/software codesign for FPGA-based systems

Hardware/software codesign for FPGA-based systems

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Annual Hawaii international conference on System Sciences (HICSS)

作者： J.M. Saul Computing Laboratory Programming Research Group Oxford University Oxford UK

A new codesign compiler called Dash (Design Automation for software and hardware) provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrised. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.

关键词： hardware Field programmable gate arrays software systems Computer architecture Design automation Application software software tools Acceleration Laboratories Hip

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Design and realization of CAN bus vehicle instrument cluster based on μ C/OS-II

Design and realization of CAN bus vehicle instrument cluster...

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2011 2nd international conference on Mechanic Automation and Control Engineering, MACE 2011

作者： Dai, Jiejie Song, Hui New Main Building D645 of Beihang University Beijing China School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9781424494392

A kind of CAN bus vehicle instrument cluster is studied and designed in this paper based on the CAN (Controller Area Network)bus technology. This vehicle instrument cluster uses MC9S12XHZ512 dual-core processor as the main controller, containing signal input module, data processing module and display module which compose the hardware platform. The software adopts the high reliability real-time kernel μ C/OS-II embedded operating system to accomplish the system's functions with modular and hierarchical *** system design adds vehicle instrument cluster to the body network and reflects the real vehicle condition by receiving,processing and displaying the data through CAN bus and vehicle sensors. This system greatly reduces design circuit and cost. © 2011 IEEE.

关键词： Control system synthesis

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FPGA-Based hardware/software codesign for Video Encoder on IoT Edge Platforms 23rd

FPGA-Based Hardware/Software Codesign for Video Encoder on...

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23rd international conference on Computational Science and Its Applications, ICCSA 2023

作者： Pham-Quoc, Cuong 268 Ly Thuong Kiet street District 10 Ho Chi Minh City Viet Nam Thu Duc Ho Chi Minh City Viet Nam

ISBN: (纸本)9783031371165

Recently, image/video-based applications have been widely used for many domains, such as traffic, medical, or robotics. In this context, IoT-based systems with video processing implemented on edge devices have been applied extensively, for example, surveillance, object detection and monitoring, or intelligent home/building systems. Although algorithms for images/videos encoder with various standards produce good results, they usually require high computing power that is limited with edge platforms. Therefore, we propose an efficient hardware/software codesign approach to accelerate the video encoder process with FPGA-based IoT edge computing platforms in this work. The design flow exploits the effectiveness of the high-level synthesis process to quickly and efficiently generate FPGA-based hardware accelerator cores to improve system performance. We use the H.264 encoder as our case study to verify the proposed design flow and evaluate the accelerator ability compared to general-purpose processors. An FPGA Ultra96-v2 edge computing board is used for conducting experiments with a certified dataset. Experimental results show that we obtain speed-ups by up to 14.9 × compared to a 4-core ARM processor. Our experimental system also saves up to 6.24 × energy consumption compared to the ARM processor. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Field programmable gate arrays (FPGA)

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An introduction to the SystemC synthesis subset standard

An introduction to the SystemC synthesis subset standard

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作者： Coussy, Philippe Takach, Andres McNamara, Michael Meredith, Mike Université de Bretagne-Sud Rue de Saint Maude Lorient Cedex 56321 France Mentor Graphics 8005 SW Boeckman Rd. Wilsonville OR 97070 United States Cadence 2655 Seely Avenue San Jose CA 95134 United States Forte Design Systems 16150 NE 85th Street Redmond WA 98052 United States

ISBN: (纸本)9781605589053

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. © 2010 ACM.

关键词： High level synthesis

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Emotion-Aware Multimedia synthesis: A Generative AI Framework for Personalized Content Generation based on User Sentiment Analysis 2

Emotion-Aware Multimedia Synthesis: A Generative AI Framewor...

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2nd international conference on Intelligent Data Communication Technologies and Internet of Things, IDCIoT 2024

作者： Sivasathiya, G. Anil Kumar, D. Harish Rangasamy, A.R. Kanishkaa, R. Chennai India

ISBN: (纸本)9798350327533

This research work introduces an innovative approach to multimedia content creation by incorporating emotion and sentiment analysis into a Generative Adversarial Network (GAN) framework. The system dynamically detects and interprets the user's emotional and sentiment cues, allowing for real-time adaptation and generation of multimedia content, including images, videos, and music. Leveraging advanced deep learning techniques, such as sentiment-aware GANs and emotion recognition through neural networks, the proposed framework establishes a seamless connection between user expression and media synthesis. By conditioning the generative process on the user's emotional state, the model learns to generate contextually relevant and emotionally resonant content. This research work encompasses an in-depth analysis of existing emotion recognition methods, the design and architecture of the proposed system, hardware and software requirements, as well as rigorous testing and performance evaluations. The outcome aims to redefine interactive multimedia experiences, empowering users to effortlessly communicate and translate the emotions into personalized and expressive digital content © 2024 IEEE.

关键词： Deep Learning Image generative AI NLP Speech Recognition

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FPGA Stream-Monitoring of Real-time Properties

FPGA Stream-Monitoring of Real-time Properties

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and System synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Baumeister, Jan Finkbeiner, Bernd Schwenger, Maximilian Torfah, Hazem Saarland Univ Campus E1-1Room 1-16-2 D-66123 Saarbrucken Germany Saarland Univ Campus E1-1Room 1-11 D-66123 Saarbrucken Germany Saarland Univ Campus E1-1Room 1-08 D-66123 Saarbrucken Germany Saarland Univ Campus E1-1Room 1-14 D-66123 Saarbrucken Germany

An essential part of cyber-physical systems is the online evaluation of real-time data streams. Especially in systems that are intrinsically safety-critical, a dedicated monitoring component inspecting data streams to detect problems at runtime greatly increases the confidence in a safe execution. Such a monitor needs to be based on a specification language capable of expressing complex, high-level properties using only the accessible low-level signals. Moreover, tight constraints on computational resources exacerbate the requirements on the monitor. Thus, several existing approaches to monitoring are not applicable due to their dependence on an operating system. We present an FPGA-based monitoring approach by compiling an RTLola specification into synthesizable VHDL code. RTLola is a stream-based specification language capable of expressing complex real-time properties while providing an upper bound on the execution time and memory requirements. The statically determined memory bound allows for a compilation to an FPGA with a fixed size. An advantage of FPGAs is a simple integration process in existing systems and superb executing time. The compilation results in a highly parallel implementation thanks to the modular nature of RTLola specifications. This further increases the maximal event rate the monitor can handle.

关键词： Stream specification languages real-time properties runtime verification FPGA

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