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2nd international conference on hardware/software codesign and systems synthesis

作者： Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology hag been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology, and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： hardware/software (HW/SW) codesign power-performance tradeoffs reconfigurable computing (RC)

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Automatic production of globally asynchronous locally synchronous systems 2nd

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2nd international conference on Embedded software (EMSOFT 2002)

作者： Girault, A Ménier, C Inria Rhone Alpes BIP Project F-38334 Saint Ismier France Ecole Normale Super Lyon F-69364 Lyon 07 France

ISBN: (纸本)354044307X

Globally Asynchronous Locally Synchronous (GALS) systems are popular both in software and hardware for specifying and producing embedded systems as well as electronic circuits. In this paper, we propose a method for obtaining automatically a GALS system from a centralised synchronous circuit. We focus on an algorithm that takes as input a program whose control structure is a synchronous sequential circuit and some distribution specifications given by the user, and gives as output the distributed program matching the distribution specifications. Since the obtained programs communicate with each other through asynchronous FIFO queues, the resulting distributed system is indeed a GALS system. We also sketch a correctness proof for our distribution algorithm, and we present how our method can be used to achieve hardware/software codesign.

关键词： globally synchronous-locally asynchronous (GALS) automatic distribution distributed architectures synchronous circuits asynchronous communications hardware/software codesign

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hardware/software codesign for FPGA-based systems

Hardware/software codesign for FPGA-based systems

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The 1999 32nd Annual Hawaii international conference on System Sciences, HICSS-32

作者： Saul, J.M. Oxford Univ Computing Lab Oxford United Kingdom

A new codesign compiler, Dash, provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrized. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.

关键词： Computer systems programming

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Special Session: Emerging Architecture Design, Control, and Security Challenges in software Defined Vehicles

Special Session: Emerging Architecture Design, Control, and ...

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2024 international conference on hardware/software codesign and System synthesis

作者： El-Fatyany, Aya Wang, Xiaohang Duggirala, Parasara Sridhar Chakraborty, Samarjit Pasricha, Sudeep Singh, Amit Kumar Zhejiang Univ Hangzhou Peoples R China Menoufia Univ Shibin Al Kawm Egypt UNC Chapel Hill Chapel Hill NC USA Colorado State Univ Ft Collins CO USA Univ Essex Colchester England

ISBN: (纸本)9798350356403;9798350356397

software Defined Vehicles (SDVs) represent a paradigm shift in the automotive industry, where vehicles are increasingly controlled and managed through software, while relying less on mechanical and hardware components. While this allows considerable flexibility in the introduction of new "smart" features and fast tracks innovations in multiple domains, it also creates new challenges and opportunities in architecture design, control, and security. By adopting modular architectures, adaptive control strategies, and robust security measures, SDVs can pave the way for a safer and more efficient future of transportation. In this paper, we cover perspectives from both, industry and academia, in this area. They provide embedded systems researchers an overview of recent developments and emerging challenges in SDV from the perspective of architecture design, control, and security. The emerging challenges also set the foundations for future research in this domain.

关键词： software defined vehicles (SDVs) Architecture design Control Robustness Security

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A table masking countermeasure for low-energy secure embedded systems

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年第7期14卷 740-753页

作者： Gebotys, Catherine H. Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada

Future wireless embedded devices will be increasingly powerful, supporting many more applications, including one of the most crucial, which is security. Although many embedded devices offer more resistance to bus probing attacks due to their compact size, susceptibility to power or electromagnetic analysis attacks must be analyzed. This paper presents a table masking countermeasure to resist differential power analysis (DPA) and differential electromagnetic analysis (DEMA). Real power and EM measurements are used to verify the countermeasure using second- and third-order DPA and DEMA attacks on a popular low-energy embedded ARM processor. Results show that the new table masking countermeasure provides increased security without large overheads of energy dissipation compared with previous countermeasures. With the emergence of security applications personal digital assistants, cellphones, and other embedded devices, low-energy countermeasures for resistance to DPA/DEMA are crucial for supporting future wireless embedded systems.

关键词： countermeasure differential electromagnetic analysis (DEMA) differential power analysis (DPA) security smartcard

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Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

Modeling operation and microarchitecture concurrency for com...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Zhu, Xinping Qin, Wei Malik, Sharad Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)1581139373

In multiprocessor-based system-on-chips (SOCs), optimizing the communication architecture is often as important-as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time;at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation-level concurrency maps to the microarchitectural-level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). Our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multiprocessing-element SOC prototypes. We show that, by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design.

关键词： bus design exploration multiprocessor system on-chip communication architecture (OCA) packet-switching network retargetable simulation simulator synthesis

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Efficient exploration of bus-based system-on-chip architectures

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年第7期14卷 681-692页

作者： Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Codesign & Parallel Proc Lab Seoul 151742 South Korea Samsung Elect Yongin 446711 Gyeonggi South Korea

Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.

关键词： communication architecture design space exploration memory allocation multitask performance estimation

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Work-in-Progress: Hierarchical Ensemble Learning for Resource-Aware FPGA Computing

Work-in-Progress: Hierarchical Ensemble Learning for Resourc...

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ACM/IEEE international conference on hardware/software codesign and System synthesis (CODES+ISSS)

作者： Wang, Hongfei Li, Jianwen He, Kun Cai, Wenjie Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Peoples R China

ISBN: (纸本)9781538655627

Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]–[4]. Despite the booming trend in building neuromorphic computing systems [2], decision trees still attract much attention in ML communities, from both software [5], [6] and hardware [1], [7], [8] approaches. A single tree model may not be as accurate as desired. One effective way to remedy this is to apply ensemble methods [5]–[7], [9]–[11], such as the Random Forest (RF) [5]. Larger tree ensembles typically improve accuracy, but demand more computation resources, especially for hardware implementation. Many methods have been proposed to address this issue. The motivation arouses from the fact that tree models usually demands much less computation resource comparing to neural networks, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT [7], [11], [12]. Moreover, due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA [1], [4], [7]–[9], [11], [13].

关键词： Radio frequency Vegetation hardware Field programmable gate arrays Forestry Minimization Computational modeling

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Design of Outdoor Recommendation Algorithm Based on User Location 2

Design of Outdoor Recommendation Algorithm Based on User Loc...

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2nd IEEE international conference on Computer and Communications (ICCC)

作者： Dang, Yang Wang, Zhongzhu Liu, Xianzhong East China Normal Univ Sch Comp Sci & Software Engn Shanghai Peoples R China East China Normal Univ Sch Comp Sci & Software Engn Software Hardware Codesign Engn Res Ctr MoE Shanghai Peoples R China

ISBN: (纸本)9781467390262

Nowaday, the rapid popularization of mobile terminals and increasing maturity of location technology are bringing new opportunities and challenges to recommendation systems. Recommendation systems need to consider user's mobility and the resulting related issues, such as the relationship between user's interests and locations, and the requirement of real-time. The problems which facing are more complex. Besides, if making good use of user's location information, can improve the performance of recommendation. In this paper, an outdoor recommendation algorithm based on user's location is proposed. When user is in a different position, using different recommendation algorithms to generate recommendations, it overcomes the cold start and sparse matrix problem which in traditional recommendation algorithms, and it also can alleviate the problem of capturing user's short-term interests in mobile environment. The experimental results show that the proposed algorithm is better than other traditional recommendation algorithms.

关键词： recommendation location cold start sparse matrix problem short-term interest

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Work-in-Progress: EAST-DNN: Expediting Architectural SimulaTions Using Deep Neural Networks

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaT...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and System synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Dutt, Arko Narasimman, Govind Jie, Lin Chandrasekhar, Vijay Ramaseshan Sabry, Mohamed M. NTU Singapore Singapore Singapore A STAR I2R Singapore Singapore Singapore

ISBN: (纸本)9781450369237

A rapid and accurate architectural simulator is a cornerstone for an efficient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 106 x speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2x better accuracy with at least 2.3x speedup compared to state-of-the-art.

关键词： Deep Neural Network hardware Accelerators

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