检索结果-内蒙古大学图书馆

16th international conference on VLSI Design/2nd international conference on Embedded systems Design

作者： Vallerio, KS Jha, NK Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)0769518680

Consumer demand and improvements in hardware have caused distributed real-time embedded systems to rapidly increase in complexity. As a result, designers faced with time-to-market constraints are forced to rely on intelligent design tools to enable them to keep up with demand These tools are continually being used earlier in the design process when the design is at higher levels of abstraction. At the highest level of abstraction are hardware/software co-synthesis tools which take a system specification as input. Although many embedded systems are described in C, the system specifications for many of these tools are often in the form of one or more task graphs. These tools are very effective at solving the co-synthesis problem using task graphs but require that designers manually transform the specification from C code to task graphs, a tedious and error-prone job. The task graph extraction tool described in this paper reduces the potential for error and the time required to design an embedded system by automating the task graph extraction process. Such a tool can drastically improve designer productivity. As far as we know, this is the first tool of its kind. It has been made available on the web.

关键词： Embedded software Embedded system Field programmable gate arrays hardware Job design Process design Productivity Real time systems software libraries software tools

来源：评论

学校读者我要写书评

暂无评论

SoC-TM: Integrated HW/SW support for transactional memory programming on embedded MPSoCs 11

SoC-TM: Integrated HW/SW support for transactional memory pr...

引用

Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and System synthesis, CODES+ISSS'11

作者： Ferri, Cesare Bahar, Iris. Marongiu, Andrea Benini, Luca Lipton, Benjamin Moreshet, Tali Herlihy, Maurice School of Engineering Brown University Providence RI 02912 United States DEIS University of Bologna Viale Risorgimento 2 40136 Bologna Italy Engineering Dept Swarthmore College Swarthmore PA 19081 United States Computer Science Dept Brown University Providence RI 02912 United States

ISBN: (纸本)9781450307154

Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP- SoCs. Our proposal leverages a hardware Transactional Memory (HTM) design, based on a dedicated HW module for conflict management, whose functionality is exposed to the software through compiler directives, implemented as an extension to the popular OpenMP programming model. To further improve ease of programming, our framework sup- ports speculative parallelism, thanks to the ability of enforcing a given commit order in hardware. Our experimental results confirm that SoC-TM is a viable and cost-effective solution for embedded MPSoCs, in terms of energy, performance and productivity. Copyright 2011 ACM.

关键词： System-on-chip

来源：评论

学校读者我要写书评

暂无评论

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年第7期14卷 667-680页

作者： Paulin, Pierre G. Pilkington, Chuck Langevin, Michel Bensoudane, Essaid Lyonnard, Damien Benny, Olivier Lavigueur, Bruno Lo, David Beltrame, Giovanni Gagne, Vincent Nicolescu, Gabriela STMicroelectronics Ottawa ON K2H 8R6 Canada Ecole Polytech Montreal PQ H3C 3A7 Canada

The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components - H/W or S/W - into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%.

关键词： multimedia computing multiprocessor interconnection parallel programming

来源：评论

学校读者我要写书评

暂无评论

Introductions to special issue on ESWEEK 2011

引用

DESIGN AUTOMATION FOR EMBEDDED systems 2013年第2期17卷 215-219页

作者： Bergamaschi, Reinaldo A. Baruah, Sanjoy Fischmeister, Sebastian Dick, Robert Madsen, Jan Gupta, Rajesh Mooney, Vincent Odysci Inc Campinas SP Brazil Univ N Carolina Dept Comp Sci Chapel Hill NC USA Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA Tech Univ Denmark Dept Informat & Math Modeling DK-2800 Lyngby Denmark Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

The Embedded systems Week (ESWEEK) is the premier scientific event in research, design and implementation of embedded systems hardware, software and tools. ESWEEK brings together three major conferences in the embedded systems area, namely: CODES+ISSS (international conference on hardware/software codesign and System synthesis, ***).

关键词：

来源：评论

学校读者我要写书评

暂无评论

Efficient exploration of bus-based system-on-chip architectures

Efficient exploration of bus-based system-on-chip architectu...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Codesign & Parallel Proc Lab Seoul 151742 South Korea Samsung Elect Yongin 446711 Gyeonggi South Korea

Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.

关键词： communication architecture design space exploration memory allocation multitask performance estimation

来源：评论

学校读者我要写书评

暂无评论

A design flow for an H.264 embedded video encoder

A design flow for an H.264 embedded video encoder

引用

ITI 3rd international conference on Information and Communications Technology, ICICT 2005 - Enabling Technologies for the New Knowledge Society

作者： Amer, Ihab Badawy, Wael Jullien, Graham Calgary Alta. T2N 1N4 Canada

ISBN: (纸本)0780392701

hardware/software codesign is a rapidly-growing research area branching from hardware synthesis. The purpose of codesign is to facilitate the design of small embedded systems, that is, those consisting of a microprocessor, for which software is required, in addition to one or more semi-custom ASICs or FPGAs. In this paper, a design flow of an H.264 HW/SW digital video encoder is introduced. A design example of a hardware 4x4 DCT-like transform and quantization block integrated with the H.264 software reference model is described.

关键词： Embedded systems

来源：评论

学校读者我要写书评

暂无评论

software-hardware cosystem brain interface desig

Software-hardware cosystem brain interface desig

引用

2nd international conference on Intelligent Informatics and Biomedical Sciences, ICIIBMS 2017

作者： Cai, Wei Wu, NanSong Shi, Frank Tong, Jialing Materials and Manufacturing Technology University of California IrvineCA United States Department of Electrical Engineering Arkansas Tech University RussellvilleAR United States School of Electrical and Computer Engineering Georgia Institute of Technology AtlantaGA United States

ISBN: (纸本)9781509066643

Brain Machine Interface (BMI) is a spike sorting provide a connection between the external behavior and neural behavior of animals. Moreover, the spike sorting is significant for stability of the advanced application. To detect neuronal activity, multichannel recording is one of major methods. This paper proposed a software-hardware co-design framework with a 16-channel neural recording. Two-stage spike detection usually included a threshold method and a nonlinear energy operator (NEO). The spike clustering used the feature extraction. This multichannel spike sorting system algorithm were verified by simulations data and experiments results. The results presented a significant improvement on feature space during spike separation, due to the discrete derivative method. © 2017 IEEE.

关键词： hardware-software codesign

来源：评论

学校读者我要写书评

暂无评论

software synthesis of middleware for heterogeneous embedded systems

Software synthesis of middleware for heterogeneous embedded ...

引用

2012 2nd international conference on Consumer Electronics, Communications and Networks, CECNet 2012

作者： Fan, Yang-Hsin Wu, Jan-Ou Wang, San-Fu Dept. of Computer Science and Information Eng. National Taitung University Taitung City Taiwan Dept. of Electronic Eng. De Lin Institute of Technology Tu-Cheng Taipei City Taiwan Dept. of Electronic Eng. Ming Chi University of Technology Taipei City Taiwan

ISBN: (纸本)9781457714153

Heterogeneous embedded systems are much more diverse in hardware architectures than ever before for processors and peripherals. On the other hand, software deployments are also varied such as service-oriented architecture (SOA), open systems interconnection (OSI) and component-based software development (CBSD). The diverse architectures of hardware and software cause problems corresponding to time-to-market, cost decrease, transparency, scalab ility, flexib ility and maintainab ility. This study proposes software synthesis of middleware which can automatically generate software for heterogeneous embedded system. Moreover, it can be used to solve problems for transparency, scalability, flexibility and maintainability. The effectiveness and feasibility of the proposed approach is demonstrated by two heterogeneous embedded systems. We design e-book system and digital photo frame system to coordinate with software synthesis of middleware on two embedded system platforms. Finally, we evaluate the correction of functionality for two heterogeneous embedded systems. © 2012 IEEE.

关键词： Middleware

来源：评论

学校读者我要写书评

暂无评论

SoC synthesis with automatic hardware software interface generation 16

SoC synthesis with automatic hardware software interface gen...

引用

16th international conference on VLSI Design/2nd international conference on Embedded systems Design

作者： Singh, A Chhabra, A Gangwar, A Dwivedi, BK Balakrishnan, M Kumar, A Tejas Networks Bangalore Karnataka India

ISBN: (纸本)0769518680

Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C alongwith its interfaces. Such synthesis system should be able to generate hardware which is easily plug-gable in various types of architectures, as well as augment the application code to automatically take advantage of this new hardware component. In this paper we address this problem and present an approach for complete SoC synthesis. We automatically generate synthesizable VHDL for the compute intensive part of the application alongwith necessary interfaces. Our approach is generic in the sense that it supports various processors and buses by keeping a generic hardware interface on one end and a dedicated one on the other The generated hardware can be used in a tightly or loosely coupled manner in terms of memory and register communication. We present the effectiveness of this approach for some commonly used image processing. spatial filter applications.

关键词： Automation Computer architecture Computer interfaces Costs hardware Image processing Registers Spatial filters System-on-a-chip Time to market

来源：评论

学校读者我要写书评

暂无评论

An introduction to the SystemC synthesis subset standard 10

An introduction to the SystemC synthesis subset standard

引用

Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Coussy, Philippe Takach, Andres McNamara, Michael Meredith, Mike Université de Bretagne-Sud Rue de Saint Maude Lorient Cedex 56321 France Mentor Graphics 8005 SW Boeckman Rd. Wilsonville OR 97070 United States Cadence 2655 Seely Avenue San Jose CA 95134 United States Forte Design Systems 16150 NE 85th Street Redmond WA 98052 United States

ISBN: (纸本)9781605589053

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. OSCI's synthesis working group (SWG) [3] has led the effort of defining the synthesis subset for SystemC that is suitable for HLS. Draft version 1.3 [4] of the document was released for public review in August 2009. While still in draft form, the released document provides guidance to both tool providers and users on the subset that is being proposed and the ability to provide feedback to the SWG on the draft. This tutorial will provide a brief introduction and three case studies on the use of HLS and the current SystemC synthesis subset draft for hardware design of digital systems.

关键词： High level synthesis

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：