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2nd international conference on hardware/software codesign and systems synthesis

作者： Gebotys, Catherine H. Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada

Future wireless embedded devices will be increasingly powerful, supporting many more applications, including one of the most crucial, which is security. Although many embedded devices offer more resistance to bus probing attacks due to their compact size, susceptibility to power or electromagnetic analysis attacks must be analyzed. This paper presents a table masking countermeasure to resist differential power analysis (DPA) and differential electromagnetic analysis (DEMA). Real power and EM measurements are used to verify the countermeasure using second- and third-order DPA and DEMA attacks on a popular low-energy embedded ARM processor. Results show that the new table masking countermeasure provides increased security without large overheads of energy dissipation compared with previous countermeasures. With the emergence of security applications personal digital assistants, cellphones, and other embedded devices, low-energy countermeasures for resistance to DPA/DEMA are crucial for supporting future wireless embedded systems.

关键词： countermeasure differential electromagnetic analysis (DEMA) differential power analysis (DPA) security smartcard

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Towards a synthesis semantics for SystemC channels 10

Towards a synthesis semantics for SystemC channels

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Grüttner, Kim Kleen, Henning Oppenheimer, Frank Rettberg, Achim Nebel, Wolfgang OFFIS Institute for Information Technology Escherweg 2 26121 Oldenburg Germany Department of Computer Science Faculty II Carl von Ossietzky University Oldenburg Ammerländer Heerstrasse 114-118 26111 Oldenburg Germany

ISBN: (纸本)9781605589053

In this paper we propose a synthesis semantics for SystemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through either primitive or hierarchical channels. We present a synthesisable replacement for SystemC primitive channels that allows deterministic access scheduling and user-constrained refinement for HW/HW and HW/SW communication. We demonstrate the feasibility of our approach through synthesis and exploration of a communication intensive packet switch design under consideration of different configurations and communication refinements.

关键词： Semantics

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An Efficient Technique for Computing Importance Measures in Automatic Design of Dependable Embedded systems 14

An Efficient Technique for Computing Importance Measures in ...

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international conference on hardware / software codesign and System synthesis (CODES+ISSS)

作者： Aliee, Hananeh Glass, Michael Khosravi, Faramarz Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781450330510

Importance measure analysis judges the relative importance of components in a system and reveals how each component contributes to the system reliability. In the design of large and complex systems, importance measure analysis can therefore be employed to guide an optimization tool which design decisions to investigate to gain higher reliability. While previous research has mainly concentrated on developing analytical importance measure techniques, the automatic and frequent computing of importance measures as required in the context of design space exploration has got very few, if any attention. This paper presents a highly efficient technique to compute the reliability and structural importance measures of components of a system. The proposed technique considers the reliability of a system implementation and subsequently analyzes the importance measures of its components based on a state-of-the-art Monte Carlo simulation. The technique can therefore estimate the importance measures of all components concurrently, highly improving the performance of the computation compared, e.g., to the well-known Birnbaum approach by the factor of 2n with n being the number of components. Moreover, we show how this algorithm can be extended to support importance measure analysis in the existence of transient faults which is essential since in future systems, transient faults are expected to cause relatively more failures than permanent faults. We integrated the proposed analysis approach in an existing multi-objective local-search algorithm that is part of an automatic system-level design space exploration which seeks for system implementations with highest reliability at lowest possible cost. Experimental results show that the proposed algorithm performs efficiently with negligible imprecision, even for large real world examples.

关键词： importance sampling search problems Birnbaum approach Monte Carlo simulation automatic design automatic system-level design space exploration complex system dependable embedded systems importance measure analysis importance measure techniques large system multiobjective local-search algorithm optimization tool permanent fault structural importance measures system implementation system reliability transient fault Algorithm design and analysis Boolean functions hardware Reliability engineering Space exploration Transient analysis Computer-Aided Design transient fault system implementation permanent fault Space Exploration Algorithm design and analysis Reliability engineering tabu search Complex systems Transient analysis Boolean functions importance sampling Monte Carlo technique Computer hardware

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Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2006年第7期14卷 707-716页

作者： Zhu, Xinping Qin, Wei Malik, Sharad Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

In multiprocessor-based system-on-chips (SOCs), optimizing the communication architecture is often as important-as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time;at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation-level concurrency maps to the microarchitectural-level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). Our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multiprocessing-element SOC prototypes. We show that, by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design.

关键词： bus design exploration multiprocessor system on-chip communication architecture (OCA) packet-switching network retargetable simulation simulator synthesis

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An Innovation Tool-chain For synthesis and Implementation of Xilinx FPGA Devices 2

An Innovation Tool-chain For Synthesis and Implementation of...

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2nd IEEE international conference on Integrated Circuits and Microsystems (ICICM)

作者： Zuo, Yi He, Anping Li, Caihong Yu, Lvying Lanzhou Univ Sch Informat Sci & Engn Lanzhou Gansu Peoples R China

ISBN: (纸本)9781538635063

synthesis and implementation are two fundamental steps of the hardware design. Mountains of work in this area synthesize and implement your design from hardware Description Language (HDL) description to the target FPGA device. We present ISE plus Customized P&R, a tool-chain converting Verilog designs into XDL that contains Xilinx FPGA implement modules. A key aspect of this tool-chain is that it both embraces the efficient optimal capacity of synthesizing commercial FPGA Design Suite and the flexible bottom control ability for the implementation of the open-source third-part software. Moreover, this tool-chain can automatically generate customized placement and routing, which provided a feasibility to synthesize and implement asynchronous FPGA designs in bulk without the manual labor.

关键词： place and route tool-chain for synthesis and implementation netlist translation

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A circuit representation technique for automated circuit design

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IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION 1999年第3期3卷 205-219页

作者： Lohn, JD Colombano, SP Caelum Res Corp Moffett Field CA 94035 USA NASA Ames Res Ctr Div Computat Sci Moffett Field CA 94035 USA

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit-constructing primitives arranged in a linear sequence, This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation.

关键词： analog circuit synthesis automated design circuit representation genetic algorithms

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software optimization for MPSoC: A MPEG-2 decoder case study 08

Software optimization for MPSoC: A MPEG-2 decoder case study

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and System synthesis, CODES+ISSS 2008

作者： Cheung, Eric Hsieh, Harry Balarin, Felice Dept. of Computer Science and Engineering University of California Riverside Riverside CA 92521 United States Cadence Design Systems San Jose CA 95134 United States

ISBN: (纸本)9781605584706

Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, traditional profiling on individual processors cannot capture useful execution information to assist software optimization. A new method to model parallel executions of interacting programs is needed. In this paper, we consider the software optimization problem for throughput-constrained MPSoC designs. We define the "longest delay path" as a sequence of steps leading to a throughput constraint violation and propose an algorithm to build up the path dynamically during simulation. Using an industrial-strength MPEG-2 decoder design in our case study and custom instructions for software optimization, we show that we can optimize the software efficiently in MPSoC designs using frequently executed statement information from the longest delay path. Copyright 2008 ACM.

关键词： Decoding

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High speed GAML-based phylogenetic tree reconstruction using HW/SW codesign 2

High speed GAML-based phylogenetic tree reconstruction using...

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2nd international Computational systems Bioinformatics conference

作者： Mak, TST Lam, KP Chinese Univ Hong Kong Dept Syst Engn & Engn Management Sha Tin 100083 Peoples R China

ISBN: (纸本)0769520006

Heuristics for reconstructing the phylogenetic tree of DNA sequences based on maximum likelihood are computationally expensive. The tree evaluation function that calculates the likelihood value for each tree topology dominates the time in searching the optimal tree. We developed a hybrid hardware/software (HW/SW) system for solving the phylogenetic tree reconstruction problem using the Genetic Algorithm for Maximum Likelihood (GAML) approach. The GAML is partitioned into a genetic algorithm (GA) and a fitness evaluation function, with the SW handling the GA and the HW evaluating the maximum likelihood function. This approach exploits the flexibility of software and the speed up of high performance hardware. An efficient Field Programmable Gate Arrays (FPGA) implementation for the required computation on evolution tree topology fitness evaluation is proposed The complete high-level digital design is developed and Xilinx's Java-based JBits toolkit is used for constructing a BRAM interface for digital process synchronization control and GA chromosomes transmission between a workstation and the Xilinx Virtex-800 FPGA Processor. This implementation provides approximately 30 to 100 times in speedup improvement when compared to a software solution.

关键词： DNA sequences

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An approach to hardware/software partitioning for multiple hardware devices model

An approach to hardware/software partitioning for multiple h...

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2nd international conference on software Engineering and Formal Methods

作者： Pu, GG Zhao, XP Wang, SL Qiu, ZY He, JF Wang, Y Peking Univ Sch Math LMAM Beijing 100871 Peoples R China

ISBN: (纸本)076952222X

Computer aided hardware/software partitioning is one of the key challenges in hardware/software co-design. This paper describes a new approach to hardware/software partitioning for multiple hardware-devices model. The partitioning is transformed into a reachability problem of timed automata, and the optimal solution can be obtained by means of an optimal reachibility algorithm. To relax the initial condition of partitioning for optimization, two algorithms are designed to explore the dependency. relations among processes in the sequential specification. Some experiments are conducted with model checker UPPAAL to show our approach is both effective and efficient.

关键词： hardware-software codesign reachability analysis program diagnostics automata theory program verification multiple hardware devices model computer aided hardware-software partitioning hardware-software codesign reachability problem timed automata optimal reachability algorithm dependency relations sequential specification UPPAAL model checker

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Model-based codesign of critical embedded systems

Model-based codesign of critical embedded systems

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2nd international Workshop on Model Based Architecting and Construction of Embedded systems, ACES-MB 2009 - Held as Part of the 2009 international conference on Model Driven Engineering Languages and systems, MoDELS 2009

作者： Bozzano, Marco Cimatti, Alessandro Katoen, Joost-Pieter Nguyen, Viet Yen Noll, Thomas Roveri, Marco Fondazione Bruno Kessler Italy RWTH Aachen University Germany

We present a comprehensive methodology for the specification and analysis of critical embedded systems. The methodology is based on an architectural design language that enables modeling of both software and hardware components, timed and hybrid behavior, faulty behavior and degraded modes of operation, error propagation and recovery. The methodology is supported by an integrated platform, implemented on top of state-of-the-art tools, that provides verification capabilities ranging from requirements analysis to functional verification, safety assessment, performability evaluation, diagnosis and diagnosability.

关键词： Embedded systems

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