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Scratchpad allocation for concurrent embedded software 08

Scratchpad allocation for concurrent embedded software

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and System synthesis, CODES+ISSS 2008

作者： Suhendra, Vivy Roychoudhury, Abhik Mitra, Tulika Department of Computer Science National University of Singapore Singapore

ISBN: (纸本)9781605584706

software-controlled scratchpad memory is increasingly employed in embedded systems as it offers better timing predictability compared to caches. Previous scratchpad allocation algorithms typically consider single process applications. But embedded applications are mostly multi-tasking with real-time constraints, where the scratchpad memory space has to be shared among interacting processes that may preempt each other. In this paper, we develop a novel dynamic scratchpad allocation technique that takes these process interferences into account to improve the performance and predictability of the memory system. We model the application as a Message Sequence Chart (MSC) to best capture the interprocess interactions. Our goal is to optimize the worst-case response time (WCRT) of the application through runtime reloading of the scratchpad memory content at appropriate execution points. We propose an iterative allocation algorithm that consists of two critical steps: (1) analyze the MSC along with the existing allocation to determine potential interference patterns, and (2) exploit this interference information to tune the scratchpad reloading points and content so as to best improve the WCRT. We evaluate our memory allocation scheme on a real-world embedded application controlling an Unmanned Aerial Vehicle (UAV). Copyright 2008 ACM.

关键词： Embedded systems

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software library functions implementation of a customized High-Level synthesis environment

Software library functions implementation of a customized Hi...

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2013 2nd international conference on Frontiers of Energy and Environment Engineering, ICFEEE 2013

作者： Dang, Lin-Yu Pang, Jian-Min Yu, Jin-Tao Yang, Jin State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou China

ISBN: (纸本)9781138000513

Compared with traditional hardware Design Languages (HDL) programming, High-Level synthesis (HLS) can reduce the design difficulty of reconfigurable system. Most HLS tools target for systems on programmable chips, and do not support loosely coupled reconfigurable computers. This paper presents a method for using HLS results in some loosely coupled systems with Ethernet as means of communication. software processes run on general purpose processors instead of embedded CPUs, and there are only hardware processes on the FPGAs. software and hardware processes communicate over Ethernet with a self-designed reliable protocol. This paper mainly discusses the software part of this method. Finally, we present some primary experiment results on the PRCA (Proactive Reconfigurable Computing Architecture) prototype platform created by our research group. The results indicate that the method is feasible. © 2014 Taylor & Francis Group, London.

关键词： General purpose computers

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Work-in-Progress: Cooperative MLP-Mixer Networks Inference On Heterogeneous Edge Devices through Partition and Fusion

Work-in-Progress: Cooperative MLP-Mixer Networks Inference O...

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international conference on Compilers, Architecture, and synthesis for Embedded systems (CASES)

作者： Li, Yiming Gu, Shouzhen Chen, Mingsong East China Normal Univ MoE Res Ctr Hardware Software Codesign Technol & Shanghai 200062 Peoples R China

ISBN: (数字)9781665472968

ISBN: (纸本)9781665472968

As a newly proposed DNN architecture, MLP-Mixer is attracting increasing attention due to its competitive results compared to CNNs and attention-base networks in various tasks. Although MLP-Mixer only contains MLP layers, it still suffers from high communication costs in edge computing scenarios, resulting in long inference time. To improve the inference performance of an MLP-Mixer model on correlated resourceconstrained heterogeneous edge devices, this paper proposes a novel partition and fusion method specific for MLP-Mixer layers, which can significantly reduce the communication costs. Experimental results show that, when the number of devices increases from 2 to 6, our partition and fusion method can archive 1.01-1.27x and 1.54-3.12x speedup in scenarios with heterogeneous and homogeneous devices, respectively.

关键词： MLP-Mixer DNN Inference Edge Intelligence

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ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors

ISEGEN: An iterative improvement-based ISE generation techni...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Biswas, Partha Banerjee, Sudarshan Dutt, Nikil D. Pozzi, Laura Ienne, Paolo MathWorks Inc Natick MA 01760 USA Univ Calif Irvine Donald Bren Sch Informat & Comp Sci Ctr Embedded Syst Irvine CA 92697 USA Univ Lugano Dept Informat CH-6900 Lugano Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Processor Architecture Lab CH-1015 Lausanne Switzerland

Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Experimental results on a number of MediaBench, EEMBC, and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20 x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application by effectively exploiting its regular structure.

关键词： application-specific processors hardware-software partitioning instruction set extensions

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Research on FPGA Based Evolvable hardware Chips for Solving Super-High Dimensional Equations Group

Research on FPGA Based Evolvable Hardware Chips for Solving ...

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2nd international conference on High Performance Computing and Applications

作者： Li, Kangshun Guo, Zhaolu Chen, Zhangxin Ge, Baoshan South China Agr Univ Sch Informat Guangzhou 510642 Guangdong Peoples R China Jiangxi Univ Sci & Technol Sch Informat Engn Ganzhou 341000 Peoples R China Univ Calgary Dept Chem & Petr Engn Calgary AB Canada Chinese Acad Sci Inst Automat Beijing 100190 Peoples R China Univ Calgary Schulich Sch Engn Dept Chem & Petr Engn Calgary AB T2N 1N4 Canada

ISBN: (纸本)9783642118418

Solving a super-high dimensional equations group is widely used in science and engineering, but the slow solution speed is the biggest problem researchers face. Research on FPGA based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC) is proposed in this paper. These chips can be implemented on a million-gate scale FPGA chip. The core architecture of SHDESC is a systolic array which consists of thousands of special arithmetic units and can execute many super-high dimensional matrix operations parallelly in short time as well as really achieve the purpose of high speed solution in hardware/software codesign. The experiments show that these chips can achieve high precision results in a short period of time to solve a super-high dimensional equations group.

关键词： Evolvable hardware super-high dimension equations group FPGA hardware/software codesign systolic array

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FastFwd: An efficient hardware acceleration technique for trace-driven network-on-chip simulation 10

FastFwd: An efficient hardware acceleration technique for tr...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Krishnaiah, Gummidipudi Silpa, B.V.N. Panda, Preeti Ranjan Kumar, Anshul Dept. of CSE IIT Delhi New Delhi India

ISBN: (纸本)9781605589053

We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speeds on host machines have motivated the need for hardware accelerators for speeding up the simulation. For example, simulation of applications with real life problem sizes could take weeks on a host machine. FPGA acceleration is a promising strategy for speeding up NoC simulations by several orders of magnitude. However, it is required to simulate a few billion network transactions of the application during NoC exploration, and this could still take tens of minutes even with an FPGA-based emulator. With the increasing complexity of architectures and applications, reducing emulation time is a key concern. We propose a technique, FastFwd, to minimize emulation time by efficiently identifying and eliminating redundant cycles during a trace-based NoC simulation. We have studied the implications of the additional FPGA hardware required for implementing our technique. A naïve implementation could lead to poor scalability and increase the required DRAM bandwidth, both of which ultimately impact the emulation speed negatively. We propose a hierarchical controller architecture to resolve the scalability issue, and a compressed representation of traces for mitigating the increased DRAM bandwidth requirement. Our experiments with several benchmarks have shown that the FPGA emulation with our technique reduces the average emulation time by a factor of 2 when compared to a conventional emulation.

关键词： Network-on-chip

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Digital Assistant For The Blind 2

Digital Assistant For The Blind

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2nd international conference for Convergence in Technology (I2CT)

作者： Bose, Prince Malpthak, Apurva Bansal, Utkarsh Harsola, Ashish Fr Conceicao Rodrigues Inst Technol Vashi 400703 India

ISBN: (纸本)9781509043071

The blind and the visually impaired have little to no internet presence because of the absence of cheap solutions to get them online which can be both, hardware and software. Existing technology used for enabling the blind or visually impaired to use the Internet or any digital form of information is dependent on Braille displays and keyboards which are expensive and scarce. Another shortcoming of existing technology is that out of all the visually impaired population, less than 2% know how to interpret Braille. Hence a voice controlled system for the blind and the visually impaired was designed, which transceives information in the form of audio. It enables the user to receive and send emails, access daily news, weather forecast, set reminders and alarms and make notes.

关键词： Voice assistant Speech Recognition Low cost Internet Speech synthesis Blind Visually Challenged Raspberry Pi

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Compositional Design of Multi-Robot systems Control software on ROS

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systems 2019年第5期18卷 1-24页

作者： Spellini, Stefano Lora, Michele Fummi, Franco Chattopadhyay, Sudipta Univ Verona Dept Comp Sci Str Grazie 15 I-37134 Verona Italy Singapore Univ Technol & Design ISTD 8 Somapah Rd Singapore 487372 Singapore

This paper presents a methodology that relies on Assume-Guarantee Contracts to decompose the problem of synthesizing control software for a multi-robot system. Initially, each contract describes either a component (e.g., a robot) or an aspect of the system. Then, the design problem is decomposed into different synthesis and verification sub-problems, allowing to tackle the complexity involved in the design process. The design problem is then recomposed by exploiting the rigorousness provided by contracts. This allows us to achieve system-level simulation capable to be used for validating the entire design. Once validated, the software synthesized during the process can be integrated into Robot Operating System (ROS) nodes and executed using state-of-the-practice packages and tools for modern robotic systems. We apply the methodology to generate a control strategy for an autonomous goods transportation system. Our results show a massive reduction of the time required to obtain automatically the control software implementing a multi-robot mission.

关键词： Contract-based design robotic operating system

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hardware/software partitioning for multi-function systems

Hardware/software partitioning for multi-function systems

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Proceedings of the 1997 IEEE/ACM international conference on Computer-Aided Design, ICCAD

作者： Kalavade, Asawaree Subrahmanyam, P.A. Bell Lab Holmdel NJ United States

We are interested in optimizing the design of multi-function embedded systems that run a pre-specified set of applications, such as multi-standard audio/video codecs and multi-system phones. Such systems usually have stringent performance constraints and tend to have mixed hardware-software implementations. The current state of the art in the hardwares/software codesign of such systems is to design for each application separately. This often leads to application-specific sub-optimal decisions and inconsistent mappings of common nodes in different applications. We use these as the guiding principles to formulate, as a code-sign problem, the design and synthesis of an efficient hardware-software implementation for a multi-function embedded system. Our solution methodology is to first identify nodes that represent similar functionality across different application. Such `common' nodes are characterized by several metrics. These metrics are quantified and used by a hardware/software partitioning tool to map common nodes to the same resource as far as possible. We demonstrate how this is achieved by modifying a traditional partitioning algorithm (GCLP) used to partition single applications. The overall result of the system-level partitioning process is (1) a hardware or software or software mapping and (2) a schedule for execution for each node within the application set. On an example set consisting of three video applications, we show that the solution obtained by the use of our method is 38% smaller than that obtained when each application is considered independently.

关键词： Multiprocessing systems

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System design extreme makeover 05

System design extreme makeover

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3rd ACM/IEEE international conference on Formal Methods and Models for Co-Design

作者： Gajski, DD Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)0780392272

With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. In order to find a solution for the system-level design flow, we must look at the system gap between SW and HW designs and then try to bridge this gap by developing a design flow that is based on common principles applicable to software and hardware. In order to achieve this design flow we can define design process by using the concepts found in standard algebras which, in turn, allows us to define design models more formally with clean unambiguous semantics. Such clean semantics allows automatic model generation, simplifies synthesis algorithms and verification techniques.

关键词： system-level design flow formal verification technique hardware-software codesign automatic model generation

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