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A hardware Structure of HEVC Intra Prediction 2

A Hardware Structure of HEVC Intra Prediction

引用

2nd international conference on Information Science and Control Engineering

作者： Lu, Wei Yu, Ningmei Nan, Jianghan Wang, Dongfang Xian Univ Technol Dept Elect Engn Xian Peoples R China

ISBN: (纸本)9781467368506

In this paper a parallel hardware structure of ASIC for HEVC intra prediction encoding is proposed. This structure by analyzing software algorithm, according to the characteristics of the ASIC implementation of parallelization, designs the DC, a planar, horizontal and vertical Angle prediction hardware structure of the parallel processing, and finished the calculation of SATD. A parallel prediction hardware structure is designed in order to improve the computational efficiency. SATD calculated using a set of registers in the shift and 4-2 compression method implements the pipeline of processing, greatly improving the throughput rate and computational efficiency. After logic synthesis using the SMIC0.13 mu m standard cell library, simulation results show that the proposed architecture of 4 4 logic gates for 29.8K, on-chip cache to 6.8 KB. At 300MHz, real-time processing 3840 2160@25fps sequence of images, extremely suit for VLSI HD encoder.

关键词： HEVC Intra Prediction VLSI

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Methodology for attack on a Java-based PDA

Methodology for attack on a Java-based PDA

引用

CODES+ISSS 2006: 4th international conference on hardware software codesign and System synthesis

作者： Gebotys, C.H. White, B.A. Department of Electrical and Computer Engineering University of Waterloo Waterloo Ont. N2L3G1 Canada

ISBN: (纸本)1595933700

Although mobile Java code is frequently executed on many wireless devices, the susceptibility to electromagnetic (EM) attacks is largely unknown. If analysis of EM waves emanating from the wireless device during a cryptographic computation does leak sufficient information, it may be possible for an attacker to reconstruct the secret key. Possession of the secret cryptographic key would render all future wireless communications insecure and cause further potential problems such as identity theft. Despite the complexities of a Java-based PDA device, this paper proposes and verifies a methodology which confirms EM attacks are possible. The proposed methodology involves pre-characterization of the PDA device through SEMA, thresholding, pattern recognition, and frequency-based DEMA. Results are repeatable over several different secret keys. Unlike previous research the new methodology does not require perfect alignment of EM frames and demonstrates robustness in the presence of a complex embedded system. This research is important for future wireless embedded systems which will increasingly demand higher levels of security. © Copyright 2006 ACM.

关键词： Personal digital assistants

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CMSM: An efficient and effective code management for software managed multicores

CMSM: An efficient and effective code management for softwar...

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11th ACM/IEEE international conference on hardware/software codesign and System synthesis, CODES+ISSS 2013

作者： Bai, Ke Lu, Jing Shrivastava, Aviral Holton, Bryce Compiler Microarchitecture Laboratory Arizona State University Tempe AZ 85287 United States

ISBN: (纸本)9781479914173

As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. software Managed Multicore (SMM) architectures are one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task mapped to a core do not fit on its local scratchpad memory, then explicit code and data management is required. In this paper, we solve the problem of efficiently managing code on an SMM architecture. We extend the state of the art by: i) correctly calculating the code management overhead, ii) even in the presence of branches in the task, and iii) developing a heuristic CMSM (Code Mapping for software Managed multicores) that results in efficient code management execution on the local scratchpad memory. Our experimental results collected after executing applications from MiBench suite [1] on the Cell SPEs (Cell is an SMM architecture) [2], demonstrate that correct management cost calculation and branch consideration can improve performance by 12%. Our heuristic CMSM can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks. © 2013 IEEE.

关键词： Embedded systems

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Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow met...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and System synthesis

作者： Lim, Pilok Kim, Taewhan School of Electrical Enginnering and Computer Science Seoul National University Seoul Korea Republic of

ISBN: (纸本)1595933700

Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1?C and 11.8?C lower peak temperature on the average, compared to that of the conventional low-power and thermalaware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively. © Copyright 2006 ACM.

关键词： Microprocessor chips

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R²Cache: Reliability-Aware Reconfigurable Last-Level Cache Architecture for Multi-Cores

R<SUP>2</SUP>Cache: Reliability-Aware Reconfigurable Last-Le...

引用

IEEE/ACM international conference on hardware/software codesign and System synthesis (CODES+ISSS)

作者： Kriebel, Florian Subramaniyan, Arun Rehman, Semeen Ahandagbe, Segnon Jean Bruno Shafique, Muhammad Henkel, Joerg Karlsruhe Inst Technol Chair Embedded Syst Karlsruhe Germany

ISBN: (纸本)9781467383219

On-chip last-level caches in multicore systems are one of the most vulnerable components to soft errors. However, vulnerability to soft errors highly depends upon the parameters and configuration of the last-level cache, especially when executing different applications. Therefore, in a reconfigurable cache architecture, the cache parameters can be adapted at run-time to improve its reliability against soft errors. In this paper we propose a novel reliability-aware reconfigurable last-level cache architecture (R(2)Cache) for multicore systems. It provides reliability-wise efficient cache configurations (i. e. cache parameter selection and cache partitioning) for different concurrently executing applications under user-provided tolerable performance overheads. To enable run-time adaptations, we also introduce a lightweight online vulnerability predictor that exploits the knowledge of performance metrics like number of L2 misses to accurately estimate the cache vulnerability to soft errors. Based on the predicted vulnerabilities of different concurrently executing applications in the current execution epoch, our run-time reliability manager reconfigures the cache such that, for the next execution epoch, the total vulnerability for all concurrently executing applications is minimized. In scenarios where single-bit error correction for cache lines may be afforded, vulnerability-aware reconfigurations can be leveraged to increase the reliability of the last-level cache against multi-bit errors. Compared to state-of-the-art, the proposed architecture provides 24% vulnerability savings when averaged across numerous experiments, while reducing the vulnerability by more than 60% for selected applications and application phases.

关键词： cache storage multiprocessing systems reconfigurable architectures reliability R2Cache lightweight online vulnerability predictor multicore systems on-chip last-level caches reliability-aware reconfigurable last-level cache architecture soft errors Circuit faults Error analysis Estimation Measurement Predictive models Random access memory Reliability Cache memory Circuit faults Multiprocessing systems random access machine cache storage Reconfigurable architectures Prediction models Error analysis Runtime

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B2Sim:: A fast micro-architecture simulator based on basic block characterization

B2Sim:: A fast micro-architecture simulator based on basic b...

引用

CODES+ISSS 2006: 4th international conference on hardware software codesign and System synthesis

作者： Lee, Wonbok Patel, Kimish Pedram, Massoud Department of Electrical Engineering University of Southern California Los Angeles CA 90089

ISBN: (纸本)1595933700

State-of-the-art architectural simulators support cycle accurate pipeline execution of application programs. However, it takes days and weeks to complete the simulation of even a moderate-size program. During the execution of a program, program behavior does not change randomly but changes over time in a predictable/periodic manner. This behavior provides the opportunity to limit the use of a pipeline simulator. More precisely, this paper presents a hybrid simulation engine, named B2Sim for (cycle-characterized) Basic Block based Simulator, where a fast cache simulator e.g., sim-cache and a slow pipeline simulator e.g., sim-outorder are employed together. B2Sim reduces the runtime of architectural simulation engines by making use of the instruction behavior within executed basic blocks. We have integrated B 2Sim into SimpleScalar and have achieved on average a factor of 3.3 times speedup on the SPEC2000 benchmark and Media-bench programs compared to conventional pipeline simulator while maintaining the accuracy of the simulation results with less than 1% CPI error on average. © Copyright 2006 ACM.

关键词： Computer simulation

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A new reactive processor with architectural support for control dominated embedded systems 16

A new reactive processor with architectural support for cont...

引用

16th international conference on VLSI Design/2nd international conference on Embedded systems Design

作者： Roop, PS Salcic, Z Biglari-Abhari, M Bigdeli, A Univ Auckland Dept EEE Auckland 1 New Zealand

ISBN: (纸本)0769518680

Control dominated embedded systems, have to be designed for fast reaction to asynchronous external events occurring in the environment. Such systems must be able to perform signal emission, signal polling, preemption and priority resolution efficiently. Current microprocessors and microcontrollers, however, have no direct support for such tasks and employ indirect mechanisms such as polling (via a port) and interrupts. In this paper we propose a new processor core having architectural support for reactivity at the instruction level. The new processor core (called REFLIX) is an extension of an existing open source processor (FLIX) core with additional instructions to support reactivity. Initial benchmarking results (for some control dominated programs) show that. REFLIX performs, on an average, 5.92 times faster compared to FLIX and has 77% code size reduction when compared to some conventional processors.

关键词： Application software Communication system control Control system synthesis Control systems Embedded system hardware Microcontrollers Microprocessors Signal processing Signal resolution

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Compositional Design of Multi-Robot systems Control software on ROS

Compositional Design of Multi-Robot Systems Control Software...

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and System synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Spellini, Stefano Lora, Michele Fummi, Franco Chattopadhyay, Sudipta Univ Verona Dept Comp Sci Str Grazie 15 I-37134 Verona Italy Singapore Univ Technol & Design ISTD 8 Somapah Rd Singapore 487372 Singapore

This paper presents a methodology that relies on Assume-Guarantee Contracts to decompose the problem of synthesizing control software for a multi-robot system. Initially, each contract describes either a component (e.g., a robot) or an aspect of the system. Then, the design problem is decomposed into different synthesis and verification sub-problems, allowing to tackle the complexity involved in the design process. The design problem is then recomposed by exploiting the rigorousness provided by contracts. This allows us to achieve system-level simulation capable to be used for validating the entire design. Once validated, the software synthesized during the process can be integrated into Robot Operating System (ROS) nodes and executed using state-of-the-practice packages and tools for modern robotic systems. We apply the methodology to generate a control strategy for an autonomous goods transportation system. Our results show a massive reduction of the time required to obtain automatically the control software implementing a multi-robot mission.

关键词： Contract-based design robotic operating system

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A DST hardware structure of HEVC 2

A DST hardware structure of HEVC

引用

2nd international conference on Information Science and Control Engineering

作者： Nan, Jianghan Yu, Ningmei Lu, Wei Wang, Dongfang Xian Univ Technol Dept Elect Engn Xian Peoples R China

ISBN: (纸本)9781467368506

HEVC(High Efficiency Video Coding) is a new generation of video coding standard which is proposed by ITU-T VCEG and ISO/IEC MPEG for the increasingly widespread application of high-definition video. On the basis of original DCT transform of H.264, HEVC has proposed a DST transform with the size of 4x4. We design the hardware structure of pipelined DST by analyzing software algorithm, according to the parallel characteristics of the ASIC, only with shifters, addition, counters and 4-2 compression method. After logic synthesis using SMIC 0.13 mu m standard cell library, simulation results show that the proposed architecture of 4x4 DST logic gates for 7K. The design can meet the demanding of timing sequence under the circumstance of real-time processing of 3840x2160@25fps sequences of images under 300MHz, and is very suitable for VLSI HD encoder.

关键词： HEVC DST 4-2 Compressor VLSI

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A structural encoding technique for the synthesis of asynchronous circuits 2

A structural encoding technique for the synthesis of asynchr...

引用

2nd international conference on Application of Concurrency to System Design (ACSD 2001)

作者： Carmona, J Cortadella, J Pastor, E Univ Politecn Catalunya Comp Architecture Dept Barcelona Spain Univ Politecn Catalunya Software Dept Barcelona Spain

ISBN: (纸本)076951071X

This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is always guaranteed. Moreover, a set of transformations is presented for the subclass of Free-Choice Petri nets that enables the exploration of different solutions. The set of transformations is derived from previous work on Petri net synthesis. Both the encoding technique and the set of transformations preserve the property of free-choiceness, thus enabling the use of structural methods for the synthesis of asynchronous circuits. Preliminary experimental results indicate that the quality of the circuits is comparable to that obtained by methods that require an exhaustive enumeration of the state space. This novel synthesis method opens the door to the synthesis of large control specifications generated from hardware description languages.

关键词： asynchronous circuits structural synthesis Complete State Coding Petri nets

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