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parallel computing for helicopter rotor design

Parallel computing for helicopter rotor design

引用

international symposium on High Performance distributed Computing

作者： J. Manke K. Neves T. Wicks Boeing Computer Services Inc. Seattle WA USA

The high-speed computing (HSC) program was established in 1986 within Boeing Computer Services (BCS) to provide a prototypical environment which could be used to study the problem of integrating new computing technologies into Boeing. This paper summarizes work within the HSC program on parallel computing and concentrates on one application area, helicopter rotor design, as an example of how these technologies are being used to prototype critical engineering processes. The paper emphasizes: (1) The prototypical process; (2) The computing technologies which were employed; (3) Some of the issues which were addressed while investigating these technologies; and (4) The software metrics used to assess the impact of using this technology in the design process.< >

关键词： parallel processing Helicopters Prototypes Computers Software prototyping Paper technology Application software Design engineering Software metrics Process design

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200 Mega pixel rate IDCT processor for HDTV applications

200 Mega pixel rate IDCT processor for HDTV applications

引用

Proceedings of the 1993 IEEE international symposium on Circuits and Systems

作者： Kim, Chan S. Song, Sang W. Kim, Man Y. Han, Young T. Kang, Sang A. Lee, Bang W. Samsung Electronic Co Korea Republic of

ISBN: (纸本)0780312813

A high-speed video rate 8 × 8 IDCT processor using a distributed arithmetic architecture is presented in this paper. 64-point one-dimensional IDCT processing units are simultaneously operated within 8 clock cycles. With these 64 fully parallel units and 3-stage pipeline structure for each unit, latency time of this proposed architecture is only 37 cycles. Additionally, ROM banks containing IDCT coefficients are minimized to 12 by applying two pixel bits per clock. This VLSI was fabricated in 1.0 μm double metal CMOS process with 120 mm2 die area consumes approximately 3 Watt at 5 Volt operating voltage and 50 MHz master clock frequency. Since critical path delay is given as 15.5 nSec, this proposed chip has enough speed for digital HDTV applications.

关键词： High definition television

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Partial order transport service for multimedia applications: reliable service

Partial order transport service for multimedia applications:...

引用

international symposium on High Performance distributed Computing

作者： P.D. Amer C. Chassot T. Connolly M. Diaz Computer and Information Science Department University of Delaware Newark DE USA L.A.A.S. du C.N.R.S. Toulouse France

This paper introduces a partial order connection (POC) protocol. Motivated in particular by multimedia applications, POC is an end-to-end connection that provides a partial order service, that is, a service that requires some, but not all objects to be received in the order transmitted. This paper discusses R-PO, a reliable version of POC which requires that all transmitted objects are eventually delivered. A metric based on the number of linear extensions of a partial order in the presence of no lost objects is proposed to quantify different partial orders. Means for its calculation is presented when P can be modeled as a combination of sequential and/or parallel compositions of Petri-nets. This metric allows one to compare and evaluate the complexity of different partial order services.< >

关键词： Streaming media Application software Quality of service Transport protocols Information science Collaborative work Multimedia systems Multimedia communication Displays Workstations

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Programming a distributed system using shared objects

Programming a distributed system using shared objects

引用

international symposium on High Performance distributed Computing

作者： A.S. Tanenbaum H.E. Bal M.F. Kaashoek Department of Mathematics and Computer Science Vrije Universiteit Amsterdam Netherlands Laboratory for Computer Science M.I.T. Cambridge MA USA

Building the hardware for a high-performance distributed computer system is a lot easier than building its software. The authors describe a model for programming distributed systems based on abstract data types that can be replicated on all machines that need them. Read operations are done locally, without requiring network traffic. Writes can be done using a reliable broadcast algorithm if the hardware supports broadcasting; otherwise, a point-to-point protocol is used. The authors have built such a system based on the Amoeba microkernel, and implemented a language, Orca, on top of it. For Orca applications that have a high ratio of reads to writes, they measure good speedups on a system with 16 processors.< >

关键词： Hardware Central processing Unit Computer science Concurrent computing Programming profession Workstations Mathematics Laboratories Traffic control Broadcasting

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Formal method for scheduling, routing and communication protocol

Formal method for scheduling, routing and communication prot...

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international symposium on High Performance distributed Computing

作者： L.M.R. Mullin S.A. Thibault D.R. Dooling E.A. Sandberg Computer Science University of Missouri Rolla MO USA Computer Science University of Vermont Burlington VT USA

The PRAM model has been shown to be an optimal design for emulating both loose and tightly coupled multiprocessors for unit time operations. When virtual processors are required, multiplexing work to available processors is employed. This introduces a form of latency incurred by operating system overhead. Further complications arise when bandwidth creates bottlenecking of work units. G.E. Blelloch (1989) showed how to add parallel prefix operations (scans) to an extended PRAM model which uses unit step, not time operations. This paper shows how the Psi( psi ) calculus can be used to group work units, i.e. pipelining the work units, so that multiplexing is not required. The authors instead pipeline work units to processors and show how the number of processors need not be equivalent to the number of data components. Partitioning array data structures and pipelining groups of partitions to processors can minimize latency and bottlenecking on distributed message passing multiprocessing architectures.< >

关键词： Routing protocols Pipeline processing Phase change random access memory Delay Processor scheduling Operating systems Bandwidth Calculus Data structures Message passing

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A parallel lattice basis reduction for mesh-connected processor arrays and parallel complexity

A parallel lattice basis reduction for mesh-connected proces...

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international symposium on parallel and distributed processing (IPDPS)

作者： C. Heckler L. Thiele Universität des Saarlandes Lehrstuhl für Mikroelektronik Saarbruecken Germany Universittä des SaarlandesLehrstuhl für Mikroelektronik Saarbruecken Germany

Lattice basis reduction has important applications in the areas of computer algebra, cryptography and combinatorial optimization. Several efficient sequential algorithms are known. Recently, parallel algorithms have been developed but until now a formal proof for the efficiency of parallel algorithms with n/sup 2/ processors has been omitted, where n denotes the dimension of the lattice. In this paper, a variant of the well-known basis reduction algorithms is presented that is well suited for the computation with fast floating point arithmetic and for the implementation on a mesh-connected array of n/sup 2/ processors. In addition, an error analysis and a proof of the parallel efficiency is provided.< >

关键词： Lattices Concurrent computing Error analysis Floating-point arithmetic Application software Algebra parallel algorithms Polynomials Cryptography Computational geometry

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Experimental evaluation of performance and scalability of a multiprogrammed shared-memory multiprocessor

Experimental evaluation of performance and scalability of a ...

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international symposium on parallel and distributed processing (IPDPS)

作者： C. Natarajan R.K. Iyer S. Sharma Coordinated Science Laboratory Center for Reliable and High-Performance Computing Urbana IL USA

This paper investigates the performance and scalability of a shared-memory multiprocessor - the CEDAR supercomputer - in multiprogrammed environments. For the 4-cluster Cedar system, the overhead due to multiprogramming is 115% for the finegrain loop parallel applications considered. There is no appreciable variation in the overhead as the multiprogramming level is increased. We find that while a single application executing on a dedicated system achieves significant speedups as the system is scaled up, in multiprogrammed environments however, there is no performance improvement with scaling. This interplay of two factors - unequal distribution of parallel work among the tasks and increased waiting times at the barriers - is found to be the major cause of the performance loss and poor scalability in multiuser environments. We find that the barrier wait time increases sharply as we go from a dedicated environment to one where 2 applications are multiprogrammed. However, the barrier wait time decreases as the multiprogramming level is increased further, due to the increasing inequality in the parallel work distribution.< >

关键词： Scalability Analytical models Supercomputers Performance loss Concurrent computing Computer architecture High performance computing Magnetic heads parallel processing Algorithm design and analysis

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On the granularity of events when modeling program executions

On the granularity of events when modeling program execution...

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international symposium on parallel and distributed processing (IPDPS)

作者： E. Leu A. Schiper IBM Research Division Almaden Research Center San Jose CA USA Département dE28099Informatique Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

In the context of parallel and distributed programming, program execution models are required to obtain a better understanding of the behavior, properties, and characteristics of parallel and distributed applications. One commonly adopted approach consists of representing an execution as a set of events and relations that capture the ordering of the events. The main disadvantages of most existing models are (1) the gap between the user's view of the execution and the program execution model, and (2) their inability to uniquely characterize an execution in terms of program behavior. The goal of this paper is to solve these two problems by first defining a new program execution model that enables more coarse-grained events to be considered, and then determining sufficient conditions for the model to uniquely identify the sequence of local states each process goes through.< >

关键词： Concurrent computing distributed computing parallel programming Context modeling Libraries Communication standards Memory architecture Message passing Broadcasting Debugging

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An optimal distributed ear decomposition algorithm with applications to biconnectivity and outerplanarity testing

An optimal distributed ear decomposition algorithm with appl...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： A. Kazmierczak S. Radhakrishnan School of Computer Science University of Oklahama Norman OK USA

We present an asynchronous distributed algorithm to determine an ear decomposition of an arbitrary, connected, bi-directional network containing n-nodes and m-links using O(m) messages and O(n) time. Using the ear decomposition we obtain the following results: 1. The distributed ear decomposition algorithm can be used to test biconnectivity, determine biconnected components, find outpoints and bridges using O(m) messages in O(n) time. 2. The distributed ear decomposition algorithm can be used to test if a network is outerplanar using O(n) messages in O(n) time and if the network is outerplanar the embedding is also given using the same message and time complexity.< >

关键词： Ear Testing Tree graphs Application software Bridges Computer science distributed algorithms Bidirectional control Algorithm design and analysis Performance evaluation

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A data-parallel approach to the implementation of weighted medians technique on parallel/super-computers

A data-parallel approach to the implementation of weighted m...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： K.P. Lam E. Horne Computing Laboratory University of Kent Canterbury UK University of Kent Canterbury Kent GB Kent Univ. Canterbury UK

Nonlinear filters have been used in many signal processing applications, for example, to obtain optimum signal extraction or detection in the presence of random noise. The weighted median filter (WMF), of which the standard median is a special case, is a novel nonlinear technique designed for 2D image processing. A major advantage of the WMF is its flexibility in design to deal with a wide variety of properties. This paper describes a commonly used class W(4,4,1) of the WMF. AS with most nonlinear methods, the computational demands of this technique are high and require a non-trivial number of "expensive" operations. A data parallel approach for efficient implementation of the WMF is described and implemented on two architecturally dissimilar supercomputers, the Convex C3840 and the Connection Machine CM-200. An analysis of the performance obtained from these two high performance parallel platforms is presented.< >

关键词： Filters Concurrent computing Laboratories Image processing Image converters Performance analysis Control systems parallel algorithms parallel processing parallel architectures

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