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检索条件"任意字段=2nd International Symposium on Parallel and Distributed Processing and Applications"

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IMPLEMENTATIONS OF MULTILAYER NEURAL NETWORKS ON parallel ARCHITECTURES

IMPLEMENTATIONS OF MULTILAYER NEURAL NETWORKS ON PARALLEL AR...

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2nd international SPECIALISTS SEMINAR ON THE DESIGN And APPLICATION OF parallel DIGITAL PROCESSORS

作者： COSNARD, M MIGNOT, JC PAUGAMMOISY, H Ecole Normale Superieure de Lyon France

ISBN: (纸本)0852965192

Connectionist models, often known as artificial neural networks, are currently the subject of a tremendous rebirth of interest in various domains of applications. These models employ massively parallel networks of simple processing elements in order to capture some knowledge of the external world as distributed patterns of activation across their nodes. A few designers have implemented neural networks directly in special-purpose VLSI hardware following the inherent parallelism of the model and offering high speed-up over simulation and serial machines. The implementation of multilayered neural networks on two parallel architectures are studied: the Connection Machine, a SIMD type computer, and the TNode, a Transputer based MIMD computer. Various implementations are compared and experimental results and performance evaluations are presented.

关键词： Neural Networks

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2nd Annual international symposium on Algorithms, ISA 1991

2nd Annual International Symposium on Algorithms, ISA 1991

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2nd Annual international symposium on Algorithms, ISA 1991

ISBN: (纸本)9783540549451

The proceedings contain 41 papers. The special focus in this conference is on Algorithms. The topics include: Decision-making with incomplete information;maximum independent set of a permutation graph in k tracks;algorithms for square roots of graphs;distributed k-mutual exclusion problem and k-coteries;weighted random assignments with application to hashing;scheduling file transfers under port and channel constraints;substitution decomposition on chordal graphs and applications;mixed-searching and proper-path-width;short wire routing in convex grids;a new approach to knock-knee channel routing;an average case analysis of monien and speckenmeyer's mechanical theorem proving algorithm;an on-line algorithm for navigating in unknown terrain;on maintaining the width and diameter of a planar point-set online;optimal triangulations by retriangulating;an incremental algorithm for constructing shortest watchman routes;on hitting grid points in a convex polygon with straight lines;on the complexity of some hamiltonian and eulerian problems in edge-colored complete graphs;dynamic programming on intervals;combinatorial optimization through order statistics;combinatorics and algorithms of geometric arrangements;an analysis of randomized shear sort on the mesh computer;efficient parallel divide-and-conquer for a class of lnterconnection topologies;optimal specified root embedding of full binary trees in faulty hypercubes;a tight lower bound for the worst case of bottom-up heapsort;historical searching and sorting;comparison-efficient and write-optimal searching and sorting;nearest neighbors revisited;competitiveness and response time in on-line algorithms;a linear time optimal via assignment algorithm for three-dimensional channel routing;symmetry of information and one-way functions.

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Lower bounds and parallel algorithms for planar orthogonal grid drawings 3

Lower bounds and parallel algorithms for planar orthogonal g...

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Proceedings of the Third IEEE symposium on parallel and distributed processing

作者： Tomassia, R. Tollis, I.G. Vitter, J.S. Department of Computer Science Brown University Providence 02912-1910 RI United States Department of Computer Science University of Texas at Dallas Richardson 75083-0688 TX United States

ISBN: (纸本)0818623101

The paper considers the problem of constructing a planer orthogonal grid drawing (or more simply, layout) of an n-vertex graph, with the goal of minimizing the number of bends along the edges. It exhibits graphs that require Omega (n) bends in any layout, and shows that there exist optimal drawings that require Omega (n) bends and have all of them on a single edge of length Omega (n²). On the other side of the coin, it presents a parallel algorithm that runs on a CREW PRAM in O(log n) time with n/log n processors and constructs layouts with O(n) maximum edge length and O(n²) area. for biconnected graphs the number of bends is at most 2n+4, which is optimal in the worst-case. This work finds applications in VLSI layout, aesthetic graph drawing, and communication by light or microwave. © 1991 IEEE.

关键词： parallel algorithms

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distributed fault-tolerant routing on hypercubes algorithms and performance study

Distributed fault-tolerant routing on hypercubes algorithms ...

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international symposium on parallel and distributed processing (IPDPS)

作者： C.T. Liang S. Bhattacharya W.T. Tsai Computer Science Department University of Minnesota MN USA

Increasing use of hypercube systems in reliability-critical applications has made fault-tolerant communication algorithms for hypercube important. This paper describes four fault-tolerant routing algorithms for hypercubes subject to link failures, namely any/sub -/nd, sidewalk, lookahead and lookside. The principle of sidewalk and lookahead are similar to two existing approaches. Lookside is an improved version of either of them. Sidewalk, lookahead and lookside guarantee successful routing in a d-cube if the number of link failures is less than d. For higher degree of link failures, the authors measure their performance by probability of successful routing and expected routing distance using two fault distribution models, probability fault model and random fault model. Lookside demonstrates better properties than sidewalk and lookahead in that it has the highest successful routing rate with reasonable routing distance.< >

关键词： Fault tolerance Routing Hypercubes Broadcasting Fault tolerant systems Computational modeling Computer science Algorithm design and analysis Performance analysis Unicast

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Lower bounds and parallel algorithms for planar orthogonal grid drawings

Lower bounds and parallel algorithms for planar orthogonal g...

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international symposium on parallel and distributed processing (IPDPS)

作者： R. Tamassia I.G. Tollis J.S. Vitter Department of Computer Science Brown University Providence RI USA Department of Computer Science University of Texas Dallas Richardson TX USA

The paper considers the problem of constructing a planer orthogonal grid drawing (or more simply, layout) of an n-vertex graph, with the goal of minimizing the number of bends along the edges. It exhibits graphs that require Omega (n) bends in any layout, and shows that there exist optimal drawings that require Omega (n) bends and have all of them on a single edge of length Omega (n/sup 2/). On the other side of the coin, it presents a parallel algorithm that runs on a CREW PRAM in O(log n) time with n/log n processors and constructs layouts with O(n) maximum edge length and O(n/sup 2/) area. for biconnected graphs the number of bends is at most 2n+4, which is optimal in the worst-case. This work finds applications in VLSI layout, aesthetic graph drawing, and communication by light or microwave.< >

关键词： parallel algorithms Compaction Computer science Phase change random access memory Very large scale integration Microwave communication Microwave circuits Contracts Algorithm design and analysis Polynomials

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A high speed systolic architecture for labeling connected components in an image

A high speed systolic architecture for labeling connected co...

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international symposium on parallel and distributed processing (IPDPS)

作者： N. Ranganathan R. Mehrotra S. Subramaniam Department of Computer Science & Engineering University of South Florida Tampa FL USA Center for Robotics and manufacturing Systems Department of Computer Science University of Kentucky Lexington KY USA

Connected components detection and labeling is an essential step in many image analysis techniques. The efficiency of the connected components labeling algorithm is critical for many image processing and machine vision applications that require real time response. The advances in the areas of parallel processing and VLSI technology can be exploited in designing hardware algorithms of high speed and throughput. The authors propose a systolic algorithm and architecture for finding connected components in an image. The architecture is simple and can be implemented as a special purpose VLSI chip. Although, the algorithm has a time complexity of O(N/sup 2/), this is in terms of the actual clock cycle which is estimated as 25 nano seconds. The proposed hardware can process a 128*128 image on 0.85 msec and uses 128 processors where as the MPP requires 94.6 msec with 16384 processors. The only special purpose hardware that exists due to X.D. Yang (1988) requires 300 msec to label a 512*512 image which can be accomplished in about 13.5 msec using the authors' proposed hardware.< >

关键词： Labeling Hardware Very large scale integration Image analysis Image processing Machine vision parallel processing Algorithm design and analysis Throughput Clocks

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CONCEPTS And METHODS FOR THE OPTIMIZATION OF distributed DATA-processing 90

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2nd international SYMP ON DATABASES IN parallel And distributed SYSTEMS ( DPDS 90 )

作者： JABLONSKI, S RUF, T WEDEKInd, H Department of Computer Science VI (Data Base Systems) University of Erlangen-Nuernberg Martensstrasse 3 D-8520 Erlangen

ISBN: (纸本)0818620528

In this paper we introduce and discuss a model of distributed data processing. For this purpose, a typical application system is analyzed and divided into sub-applications. To fulfill the task of the global application, the sub-applications have to communicate in an appropriate manner by exchanging data resp. information. In our model the communication between sub-applications is split up into two steps: the offering of information by sending sub-applications, and its acceptance by receiving sub-applications. For both communication steps synchronous and asynchronous processing modes are defined. Supporting those different communication modes the cooperation between sub-applications can be defined very closely to the specific demands of the application system. This optimizes distributed data processing. At last we demonstrate the prototype implementation of a distributed data management system, which is based on the flexible communication mechanism described in the paper.

关键词： Data processing

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Fault tolerant distributed shared memory algorithms 2

Fault tolerant distributed shared memory algorithms

引用

2nd IEEE symposium on parallel and distributed processing, SPDP 1990

作者： Stumm, Michael Zhou, Songnian University of Toronto TorontoM5S 1A4 Canada

ISBN: (纸本)0818620870

distributed shared memory (DSM) has received increased attention as a mechanism for interprocess communication in loosely-coupled distributed systems because of its perceived advantages over direct use of message passing or remote procedure calls. One problem with most DSM algorithms proposed to date, however, is that they do not tolerate faults. The paper extends four basic DSM algorithms to tolerate single host failures and argues that this degree of fault tolerance is sufficient for most applications. It analyzes the performance behavior of the fault tolerant DSM algorithms and shows that for some algorithms the additional overhead for fault tolerance is quite small, but that for other algorithms the extra overhead can be substantial and even unpredictable. © 1990 IEEE.

关键词： Fault tolerance

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Bin-packing adjustable rectangles and applications to task scheduling on partitionable parallel computers 2

Bin-packing adjustable rectangles and applications to task s...

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2nd IEEE symposium on parallel and distributed processing, SPDP 1990

作者： Ji, Jiahuang Jeng, Menkae Computer Science Department University of Houston HoustonTX77204 United States IBM Corporation 5600 Cottle Road San JoseCA95193 United States

ISBN: (纸本)0818620870

The problem of packing adjustable rectangles into a rectangular bin with minimum height is investigated. In this problem, the length and width of each rectangle can be changed, based on certain reshaping rules, before being packed into the bin. The problem is called packing adjustable rectangle (PAR) problem. One application of this problem is scheduling independent tasks on partitionable parallel computers. The paper investigated reshaping rules for reshaping rectangles, which are suitable to the task scheduling problem. Based on these rules, asymptotically optimal algorithms to solve the PAR problem are developed and presented. © 1990 IEEE.

关键词： Scheduling algorithms

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parallel join processing using nonclustered indexes for a shared memory multiprocessor 2

Parallel join processing using nonclustered indexes for a sh...

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2nd IEEE symposium on parallel and distributed processing, SPDP 1990

作者： Omiecinski, Edward Shonkwiler, Ron College of Computing Georgia Institute of Technology AtlantaGA30332 United States School of Mathematics Georgia Institute of Technology AtlantaGA30332 United States

ISBN: (纸本)0818620870

For a database system executing on a multiprocessor system, performance can be improved by inter-query parallelism as well as by intra-query parallelism. Since database applications tend to be 1/0 bound, it is important to minimize disk accesses, which reduce disk contention and improve performance from the context of interquery parallelism. On the other hand it is important to reduce the overall processing time of a query, which improves performance by intraquery parallelism. In this paper we examine the problem of efficient join processing on a shared memory multiprocessor, when the available access paths that are chosen (by the query optimizer) are nonclustered indexes on the joining attributes. We present two algorithms based on simple heuristics and a third algorithm based on the Monte Carlo optimization technique called simulated annealing. Experiments are performed to compare the various algorithms with an algorithm that recently appeared in the literature. © 1990 IEEE.

关键词： Simulated annealing

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