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检索条件"任意字段=2nd International Symposium on Parallel and Distributed Processing and Applications"

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High-order Line Graphs of Non-uniform Hypergraphs: Algorithms, applications, and Experimental Analysis

High-order Line Graphs of Non-uniform Hypergraphs: Algorithm...

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international symposium on parallel and distributed processing (IPDPS)

作者： Xu T. Liu Jesun Firoz Sinan Aksoy Ilya Amburg Andrew Lumsdaine Cliff Joslyn Brenda Praggastis Assefaw H. Gebremedhin University of Washington USA Washington State University USA Pacific Northwest National Lab USA Pacific Northwest National Lab USA

Hypergraphs offer flexible and robust data representations for many applications, but methods that work directly on hypergraphs are not readily available and tend to be prohibitively expensive. Much of the current analysis of hypergraphs relies on first performing a graph expansion – either based on the nodes (clique expansion), or on the hyperedges (line graph) − and then running standard graph analytics on the resulting representative graph. However, this approach suffers from massive space complexity and high computational cost with increasing hypergraph size. Here, we present efficient, parallel algorithms to accelerate and reduce the memory footprint of higher-order graph expansions of hypergraphs. Our results focus on the hyperedge-based s-line graph expansion, but the methods we develop work for higher-order clique expansions as well. To the best of our knowledge, ours is the first framework to enable hypergraph spectral analysis of a large dataset on a single shared-memory machine. Our methods enable the analysis of datasets from many domains that previous graph-expansion-based models are unable to provide. The proposed s-line graph computation algorithms are orders of magnitude faster than state-of-the-art sparse general matrix-matrix multiplication methods, and obtain approximately 2–31× speedup over a prior state-of-the-art heuristic-based algorithm for $s$ -line graph computation.

关键词： distributed processing Distribution strategy Heuristic algorithms Memory management Approximation algorithms Sparse matrices parallel algorithms

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PhD Forum: Efficient Privacy-Preserving processing via Memory-Centric Computing

PhD Forum: Efficient Privacy-Preserving Processing via Memor...

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Reliable distributed Systems

作者： Mpoki Mwaisela University of Neuchâtel Neuchâtel Switzerland

ISBN: (数字)9798331530037

ISBN: (纸本)9798331530044

Privacy-preserving computation techniques like homomorphic encryption (HE) and secure multi-party computation (SMPC) enhance data security by enabling processing on encrypted data. However, the significant computational and CPU-DRAM data movement overhead resulting from the underlying cryptographic algorithms impedes the adoption of these techniques in practice. Existing approaches focus on improving computational overhead using specialized hardware like GPUs and FPGAs, but these methods still suffer from the same processor-DRAM overhead. Novel hardware technologies that support in-memory processing have the potential to address this problem. Memory-centric computing, or processing-in-memory (PIM), brings computation closer to data by introducing low-power processors called data processing units (DPUs) into memory. Besides its in-memory computation capability, PIM provides extensive parallelism, resulting in significant performance improvement over state-of-the-art approaches. We propose a framework that uses recently available PIM hardware to achieve efficient privacy-preserving computation. Our design consists of a four-layer architecture: (1) an application layer that decouples privacy-preserving applications from the underlying protocols and hardware; (2) a protocol layer that implements existing secure computation protocols (HE and MPC); (3) a data orchestration layer that leverages data compression techniques to mitigate the data transfer overhead between DPUs and host memory; (4) a computation layer which implements DPU kernels on which secure computation algorithms are built.

关键词： Privacy Protocols Program processors Scalability Computer architecture parallel processing Hardware Multi-party computation Reliability Homomorphic encryption

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parallel Algorithms for Adding a Collection of Sparse Matrices

Parallel Algorithms for Adding a Collection of Sparse Matric...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Md Taufique Hussain Guttu Sai Abhishek Aydin Buluç Ariful Azad Indiana University Bloomington IN USA Indian Institute of Technology Bombay India Lawrence Berkeley National Laboratory Berkeley CA USA

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

We develop a family of parallel algorithms for the SpKAdd operation that adds a collection of k sparse matrices. SpKAdd is a much needed operation in many applications including distributed memory sparse matrix-matrix multiplication (SpGEMM), streaming accumulations of graphs, and algorithmic sparsification of the gradient updates in deep learning. While adding two sparse matrices is a common operation in Matlab, Python, Intel MKL, and various GraphBLAS libraries, these implementations do not perform well when adding a large collection of sparse matrices. We develop a series of algorithms using tree merging, heap, sparse accumulator, hash table, and sliding hash table data structures. Among them, hash-based algorithms attain the theoretical lower bounds both on the computational and I/O complexities and perform the best in practice. The newly-developed hash SpKAdd makes the computation of a distributed-memory SpGEMM algorithm at least 2x faster than previous state-of-the-art algorithms.

关键词： Deep learning distributed processing Instruction sets Merging Memory management Data structures Libraries

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Dalorex: A Data-Local Program Execution and Architecture for Memory-bound applications

Dalorex: A Data-Local Program Execution and Architecture for...

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IEEE symposium on High-Performance Computer Architecture

作者： Marcelo Orenes-Vera Esin Tureci David Wentzlaff Margaret Martonosi Princeton University Princeton New Jersey USA

applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching, decoupling, or pipelining can mitigate memory latency and improve core utilization, memory bottlenecks persist due to limited off-chip bandwidth. Approaches doing processing in-memory (PIM) with Hybrid Memory Cube (HMC) overcome bandwidth limitations but fail to achieve high core utilization due to poor task scheduling and synchronization overheads. Moreover, the high memory-per-core ratio available with HMC limits strong *** introduce Dalorex, a hardware-software co-design that achieves high parallelism and energy efficiency, demonstrating strong scaling with >16,000 cores when processing graph and sparse linear algebra workloads. Over the prior work in PIM, both using 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing tile holds an equal amount of data, and all memory operations are local; (2) a task-based parallel programming model where tasks are executed by the processing unit that is co-located with the target data; (3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata; (4) novel traffic-aware task scheduling hardware that maintains high core utilization; and (5) a data-placement strategy that improves work *** work proposes architectural and software innovations to provide the greatest scalability to date for running graph algorithms while still being programmable for other domains.

关键词： Technological innovation Software algorithms distributed databases Linear algebra Bandwidth Energy efficiency Software

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A Study of Graph Analytics for Massive Datasets on distributed Multi-GPUs 34

A Study of Graph Analytics for Massive Datasets on Distribut...

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34th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Jatala, Vishwesh Dathathri, Roshan Gill, Gurbinder Hoang, Loc Nandivada, V. Krishna Pingali, Keshav Univ Texas Austin Austin TX 78712 USA IIT Madras Chennai Tamil Nadu India

ISBN: (纸本)9781728168760

There are relatively few studies of distributed GPU graph analytics systems in the literature and they are limited in scope since they deal with small data-sets, consider only a few applications, and do not consider the interplay between partitioning policies and optimizations for computation and communication. In this paper, we present the first detailed analysis of graph analytics applications for massive real-world datasets on a distributed multi-GPU platform and the first analysis of strong scaling of smaller real-world datasets. We use D-IrGL, the state-of-the-art distributed GPU graph analytical framework, in our study. Our evaluation shows that (1) the Cartesian vertex-cut partitioning policy is critical to scale computation out on GPUs even at a small scale, (2) static load imbalance is a key factor in performance since memory is limited on GPUs, (3) device-host communication is a significant portion of execution time and should be optimized to gain performance, and (4) asynchronous execution is not always better than bulk-synchronous execution.

关键词： Graphics processing Units Graph processing distributed Systems Performance

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Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs distributed Systems 34

Hardware resources analysis of BNNs splitting for FARD-based...

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34th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Fiscaletti, Giorgia Speziali, Marco Stornaiuolo, Luca Santambrogio, Marco D. Sciuto, Donatella Politecn Milan Dipartimento Elettron Informaz & Bioingn DEIB Milan Italy

ISBN: (纸本)9781728174457

FPGAs have proven to be valid architectures to accelerate the inference phase of Convolutional Neural Networks (CNNs). State-of-the-art works also demonstrated that it is possible to take advantage of a distributed FPGA-base system to improve performance, power consumption and scalability of such algorithms. However, the hardware resource usage, communication, and the nodes management become main aspects when dealing with an embedded distributed scenario. In this context, FINN optimizes the FPGA-based CNNs with binarization and FARD is a framework that allows the acceleration of fog computing-based application with FPGAs. In this work, we present how to extend FARD to deal with job-based applications rather than the event-based fog computing scenario. In particular, we analyzed two PYNQ-Z1 connected each other and we implemented a distributed BNN algorithm based on FINN's CnvW2A2. Results show how hardware resources vary according to the division of the network when splitting after each convolutional layer.

关键词： Binarized Neural Networks BNN PYNQ embedded distributed

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On Overlapping Communication and File I/O in Collective Write Operation 34

On Overlapping Communication and File I/O in Collective Writ...

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34th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Feki, Raafat Gabriel, Edgar Univ Houston Dept Comp Sci Parallel Software Technol Lab Houston TX 77204 USA

ISBN: (纸本)9781728174457

Many parallel scientific applications spend a significant amount of time reading and writing data files. Collective I/O operations allow to optimize the file access of a process group by redistributing data across processes to match the data layout on the file system. In most parallel I/O libraries, the implementation of collective I/O operations is based on the two-phase I/O algorithm, which consists of a communication phase and a file access phase. This papers evaluates various design options for overlapping two internal cycles of the two-phase I/O algorithm, and explores using different data transfer primitives for the shuffle phase, including non-blocking two-sided communication and multiple versions of one-sided communication. The results indicate that overlap algorithms incorporating asynchronous I/O outperform overlapping approaches that only rely on non-blocking communication. However, in the vast majority of the testcases one-sided communication did not lead to performance improvements over two-sided communication.

关键词： Data transfer

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Demystifying the Performance of HPC Scientific applications on NVM-based Memory Systems 34

Demystifying the Performance of HPC Scientific Applications ...

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34th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Peng, Ivy Wu, Kai Ren, Jie Li, Dong Gokhale, Maya Lawrence Livermore Natl Lab Livermore CA 94550 USA Univ Calif Merced Merced CA USA

ISBN: (纸本)9781728168760

The emergence of high-density byte-addressable non-volatile memory (NVM) is promising to accelerate data- and compute-intensive applications. Current NVM technologies have lower performance than DRAM and, thus, are often paired with DRAM in a heterogeneous main memory. Recently, byte-addressable NVM hardware becomes available. This work provides a timely evaluation of representative HPC applications from the "Seven Dwarfs" on NVM-based main memory. Our results quantify the effectiveness of DRAM-cached-NVM for accelerating HPC applications and enabling large problems beyond the DRAM capacity. On uncached-NVM, HPC applications exhibit three tiers of performance sensitivity, i.e., insensitive, scaled, and bottlenecked. We identify write throttling and concurrency control as the priorities in optimizing applications. We highlight that concurrency change may have a diverging effect on read and write accesses in applications. Based on these findings, we explore two optimization approaches. First, we provide a prediction model that uses datasets from a small set of configurations to estimate performance at various concurrency and data sizes to avoid exhaustive search in the configuration space. Second, we demonstrate that write-aware data placement on uncached-NVM could achieve 2x performance improvement with a 60% reduction in DRAM usage.

关键词： Non-volatile memory Optane heterogeneous memory persistent memory byte-addressable NVM HPC

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Recorder 2.0: Efficient parallel I/O Tracing and Analysis 34

Recorder 2.0: Efficient Parallel I/O Tracing and Analysis

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34th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Wang, Chen Sun, Jinghan Snir, Marc Mohror, Kathryn Gonsiorowski, Elsa Univ Illinois Dept Comp Sci Urbana IL 61801 USA Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA

ISBN: (纸本)9781728174457

Recorder is a multi-level I/O tracing tool that captures HDF5, MPI-I/O, and POSIX I/O calls. In this paper, we present a new version of Recorder that adds support for most metadata POSIX calls such as stat, link, and rename. We also introduce a compressed tracing format to reduce trace file size and run time overhead incurred from collecting the trace data. Moreover, we add a set of post-mortem and visualization routines to our new version of Recorder that manage the compressed trace data for users. Our experiments with four HPC applications show a file size reduction of over 2x and reduced post-processing time by 20% when using our new compressed trace file format.

关键词： Compressed I/O Traces parallel I/O MPI-I/O

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Efficient MPI-based Communication for GPU-Accelerated Dask applications 21

Efficient MPI-based Communication for GPU-Accelerated Dask A...

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21st IEEE/ACM international symposium on Cluster, Cloud and Internet Computing (CCGrid)

作者： Shafi, Aamir Hashmi, Jahanzeb Maqbool Subramoni, Hari Panda, Dhabaleswar K. (DK) Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9781728195865

Dask is a popular parallel and distributed computing framework, which rivals Apache Spark to enable task-based scalable processing of big data. The Dask distributed library forms the basis of this computing engine and provides support for adding new communication devices. It currently has two communication devices: one for TCP and the other for high-speed networks using UCX-Py-a Cython wrapper to UCX. This paper presents the design and implementation of a new communication backend for Dask-called MPI4Dask-that is targeted for modern HPC clusters built with GPUs. MPI4Dask exploits mpi4py over MVAPICH2-GDR, which is a GPU-aware implementation of the Message Passing Interface (MPI) standard. MPI4Dask provides point-to-point asynchronous I/O communication coroutines, which are non-blocking concurrent operations defined using the async/await keywords from the Python's asyncio framework. Our latency and throughput comparisons suggest that MPI4Dask outperforms UCX by 6x for 1 Byte message and 4x for large messages (2 MBytes and beyond) respectively. We also conduct comparative performance evaluation of MPI4Dask with UCX using two benchmark applications: 1) sum of cuPy array with its transpose, and 2) cuDF merge. MPI4Dask speeds up the overall execution time of the two applications by an average of 3.47x and 3.11x respectively on an in-house cluster built with NVIDIA Tesla V100 GPUs for 1 - 6 Dask workers. We also perform scalability analysis of MPI4Dask against UCX for these applications on TACC's Frontera (GPU) system with upto 32 Dask workers on 32 NVIDIA Quadro RTX 5000 GPUs and 256 CPU cores. MPI4Dask speeds up the execution time for cuPy and cuDF applications by an average of 1.71x and 2.91x respectively for 1 - 32 Dask workers on the Frontera (GPU) system.

关键词： Python Dask MPI MVAPICH2-GDR Coroutines

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