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The Impact of Application Mapping on Non-random and Random Network Topologies 17

The Impact of Application Mapping on Non-random and Random N...

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IEEE Int Conf on parallel and distributed processing with applications, Big Data and Cloud Computing, Sustainable Computing and Communications, Social Computing and Networking (ISPA/BDCloud/SocialCom/SustainCom)

作者： Hu, Yao Koibuchi, Michihiro Natl Inst Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo 1018430 Japan

ISBN: (纸本)9781728143286

Due to recent artificial intelligence (AI) technology progress, more and more applications present all-to-all, irregular or unpredictable communication patterns among compute nodes in high-performance computing (HPC) systems. Traditional communication infrastructures, e.g., torus or fat-tree interconnection networks, may not handle well their matchmaking problems with these newly emerging applications. For these typical non-random network topologies, there are already many communication-efficient application mapping algorithms. However, for the above unpredictable communication patterns, it is difficult to efficiently map their applications onto the non-random network topologies. In this case, a simple optimization is to map their applications with small diameter or average shortest path length (ASPL) among the assigned compute nodes. In this context, we recommend to use random network topologies as the communication infrastructures, which have drawn increasing attention for the use of HPC interconnects. In this study, we make a comparative study to analyze the performance impact of application mapping on non-random and random network topologies. We list several application mapping policies, and compare their job scheduling performances assuming that the communication patterns are unpredictable to the computing system. Evaluations with a large compound application workload show that, when compared to non-random topologies, random topologies can reduce the average turnaround time up to 39.3% by a random connected mapping method and up to 72.1% by a diameter/ASPL-based mapping method.

关键词： High-performance computing (HPC) interconnection network topology embedding job scheduling

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Experimental applications on SRAM-based FPGA for the NanosatC-BR2 Scientific Mission 33

Experimental Applications on SRAM-based FPGA for the Nanosat...

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33rd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Benevenuti, Fabio Chielle, Eduardo Tonfat, Jorge Tambara, Lucas Kastensmidt, Fernanda Lima Zaffari, Carlos Alberto dos Santos Martins, Jodo Baptista Cupertino Durao, Otavio Santos Univ Fed Rio Grande Sul UFRGS Inst Informat PGMICRO Porto Alegre RS Brazil Santa Maria Design House SMDH Santa Maria RS Brazil Inst Nacl Pesquisas Espaciais INPE Sao Jose Dos Campos Brazil New York Univ Abu Dhabi U Arab Emirates Austrian Acad Sci Space Res Inst Graz Austria Cobham Gaisler AB Gothenburg Sweden

ISBN: (纸本)9781538655559

The use of reconfigurable devices, such as FPGAs, in nanosatellites allows the prototyping and evaluation in flight of different categories of designs of interest to the aerospace technology. It includes blending of experimental or well-proven legacy software executing on microprocessors with out-of-core accelerators and dedicated logic circuits, or even the conversion of such software to logic circuits using high-level synthesis (HLS). An additional feature discussed in this work, which is relevant to the scientific mission of the NanosatC-BR2 nanosatellite, is the use of SRAM-based FPGA as radiation particle sensor exploiting the susceptibility of SRAM memory to bit-flips caused by radiation. The process for bit-flip recording by bitstream readback is presented as well as a set of experimental designs implemented on the FPGA for data processing. As the status of these experimental designs must be reliably tracked by a supervisory circuit implemented on the same SRAM-based FPGA, errors caused by the bit-flips must be considered. Mitigation using triple modular redundancy (TMR) is analyzed using fault injection, suggesting that a fine grain distributed TMR approach can increase mission time of the supervisory module by 8x at a target reliability of 95%, but with a penalty of 40% in the estimated total power consumption of the FPGA. Conversely, a blockwise TMR approach can increase mission time of the supervisory module by 6x at the same target reliability with no increase in the estimated total power consumption.

关键词： SRAM-based FPGA nanosatellite single-event upsets fault tolerance

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Development of parallel CFD applications on distributed Memory with Chapel

Development of Parallel CFD Applications on Distributed Memo...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Matthieu Parenteau Simon Bourgault-Cote Frederic Plante Eric Laurendeau Department of Mechanical Engineering Polytechnique Montreal Montreal Canada

ISBN: (数字)9781728174457

ISBN: (纸本)9781728174570

Traditionally, Computational Fluid Dynamics (CFD) software uses Message Passing Interface (MPI) to handle the parallelism over distributed memory systems. For a new developer, such as a student or a new employee, the barrier of entry can be high and more training is required for each particular software package, which slows down the research process on actual science. The Chapel programming language offers an interesting alternative for research and development of CFD *** this paper, the developments of two CFD applications are presented: the first one as an experiment by re-writing a 2D structured flow solver and the second one as writing from scratch a research 3D unstructured multi-physics simulation software. Details are given on both applications with emphasis on the Chapel features which were used positively in the code design, in particular to improve flexibility and extend to distributed memory. Some performance pitfalls are discussed with solutions to avoid *** performance of the unstructured software is then studied and compared to a traditional open-source CFD software package programmed in C++ with MPI for communication (SU2). The results show that our Chapel implementation achieves performances similar to other CFD software written in C and C++, thus confirming that Chapel is a viable language for high-performance CFD applications.

关键词： Computational fluid dynamics Software parallel processing Reactive power Two dimensional displays C++ languages Programming

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Multi-Parameter Performance Modeling Based on Machine Learning with Basic Block Features 17

Multi-Parameter Performance Modeling Based on Machine Learni...

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作者： Hao, Meng Zhang, Weizhe Wang, Yiming Li, Dong Xia, Wen Wang, Hao Lou, Chen Harbin Inst Technol Sch Comp Sci & Technol Harbin Peoples R China Peng Cheng Lab Cyberspace Secur Res Ctr Shenzhen Peoples R China Univ Calif Dept Elect Engn & Comp Sci Merced CA USA Norwegian Univ Sci & Technol Dept Comp Sci Trondheim Norway

ISBN: (纸本)9781728143286

Considering the increasing complexity and scale of HPC architecture and software, the performance modeling of parallel applications on large-scale HPC platforms has become increasingly important. It plays an important role in many areas, such as performance analysis, job management, and resource estimation. In this work, we propose a multi-parameter performance modeling and prediction framework called MPerfPred, which utilizes basic block frequencies as features and uses machine learning algorithms to automatically construct multi-parameter performance models with high generalization ability. To reduce the prediction overhead, we propose some feature-filtering strategies to reduce the number of features in the training stage and build a serial program called BBF collector for each target application to quickly collect feature values in the prediction stage. We demonstrate the use of MPerfPred on the TianHe-2 supercomputer with six parallel applications. Results show that MPerfPred with SVR achieves better prediction than other input parameter-based modeling methods. The average prediction error and average standard deviation of prediction errors of MPerfPred are 8.42% and 6.09%, respectively. In the prediction stage, the average prediction overhead of MPerfPred is less than 0.13% of the total execution time.

关键词： performance modeling parallel application basic block feature machine learning

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22nd international Conference on Big Data Analytics and Knowledge Discovery, DaWaK 2020

22nd International Conference on Big Data Analytics and Know...

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22nd international Conference on Big Data Analytics and Knowledge Discovery, DaWaK 2020

ISBN: (纸本)9783030590642

The proceedings contain 30 papers. The special focus in this conference is on Big Data Analytics and Knowledge Discovery. The topics include: Extreme-sax: Extreme points based symbolic representation for time series classification;framework to optimize data processing pipelines using performance metrics;a scalable randomized algorithm for triangle enumeration on graphs based on sql queries;data engineering for data science: Two sides of the same coin;mining attribute evolution rules in dynamic attributed graphs;sustainable development goal relational modelling: Introducing the sdg-cap methodology;mining frequent seasonal gradual patterns;derivative, regression and time series analysis in sars-cov-2;building a competitive associative classifier;contrastive explanations for a deep learning model on time-series data;Dhe $$^applications$$ : distributed Hybrid Evolution Engine for Performance Optimizations of Computationally Intensive applications;cyberbullying detection in social networks using deep learning based models;predicting customer churn for insurance data;scalable machine learning on popular analytic languages with parallel data summarization;which bills are lobbied? predicting and interpreting lobbying activity in the us;fibs: A generic framework for classifying interval-based temporal sequences;multivariate time series classification: A relational way;behave or be detected! identifying outlier sequences by their group cohesion;detecting anomalies in production quality data using a method based on the chi-square test statistic;learning from past observations: Meta-learning for efficient clustering analyses;parallel k-prototypes clustering with high efficiency and accuracy;grand reports: A tool for generalizing association rule mining to numeric target values;self-organizing map for multi-view text clustering;expected vs. unexpected: Selecting right measures of interestingness.

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Dynamic Heterogeneous scheduling of GPU-CPU in distributed Environment 2

Dynamic Heterogeneous scheduling of GPU-CPU in Distributed E...

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2nd international Conference on Smart Systems and Inventive Technology, ICSSIT 2019

作者： Goyat, Suman Kant, Shri Dhariwal, Neha Computer Science and Engineering Sharda University Greater Noida UP India Sharda University Greater Noida UP India Computer Science and Engineering RIMT University Mandi Gobindgarh Punjab India

ISBN: (纸本)9781728121192

The technology has been growing in the field of computation so fast that the operation which takes days in old time now can be completed within few seconds. The basic need of such computing is fastest processing time of any operation by the system. The performance of any computing device is dependent on processor, memory and hardware/software behavior. Central processing Unit (CPU) is known to be the brain of computer. In any case, progressively, that brain can be raised by additional piece of Personal Computer with the GPU (Graphics processing Unit), which is alluded to as the aforementioned spirit. The fusion of a CPU with a GPU can convey the ideal estimation of framework cost, execution and power. It tends to be expressed that GPUs vary from CPUs as GPU is improved for throughput rather than idleness which can work quicker and more expense effectively than CPUs. GPUs are equipped for taking a lot of information and playing out a similar task again and again rapidly, in contrast to CPU, which will in general skip activities everywhere. distributed processing comprises of utilizations successively over a stage which have more than one computational device with various designs, for example, a manycore GPU and a multi-core CPU. By and large, the kernel performs well on the GPU as they are enhanced for a GPU's exceedingly with parallel engineering and GPU regularly provide higher pinnacle throughput per unit of time. The exploration says that GPU is definitely more superior to CPU because of its parallel design as it is made out of hundreds of cores which can deal with a huge number of threads when contrasted with CPU. Here, we will demonstrate this fact that GPU is growing its importance in High-Performance Computing (HPC) era. In this paper, we will take few applications with the historical information about the runtime of particular application taken on CPU and GPU. This historical information created from benchmarks will let help us to decide whether the tasks ar

关键词： Graphics processing unit

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NCQ-Aware I/O Scheduling for Conventional Solid State Drives 33

NCQ-Aware I/O Scheduling for Conventional Solid State Drives

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33rd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Fan, Hao Wu, Song Ibrahim, Shadi Chen, Ximing Jin, Hai Xiao, Jiang Guan, Haibing Huazhong Univ Sci & Technol Sch Comp Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Serv Comp Technol & Syst LabCluster & Grid Comp Wuhan Hubei Peoples R China INRIA IMT Atlantique LS2N Nantes France Shanghai Jiao Tong Univ Shanghai Key Lab Scalable Comp & Syst Shanghai Peoples R China

ISBN: (纸本)9781728112466

While current fairness-driven I/O schedulers are successful in allocating equal time/resource share to concurrent workloads, they ignore the I/O request queueing or reordering in storage device layer, such as Native Command Queueing (NCQ). As a result, requests of different workloads cannot have an equal chance to enter NCQ (NCQ conflict) and fairness is violated. We address this issue by providing the first systematic empirical analysis on how NCQ affects I/O fairness and SSD utilization and accordingly proposing a NCQ-aware I/O scheduling scheme, NASS. The basic idea of NASS is to elaborately control the request dispatch of workloads to relieve NCQ conflict and improve NCQ utilization. NASS builds on two core components: an evaluation model to quantify important features of the workload, and a dispatch control algorithm to set the appropriate request dispatch of running workloads. We integrate NASS into four state-of-the-art I/O schedulers and evaluate its effectiveness using widely used benchmarks and real world applications. Results show that with NASS, I/O schedulers can achieve 11-23% better fairness and at the same time improve device utilization by 9-29%.

关键词： SSD NCQ I/O scheduler concurrent I/O

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OpenMP4.5-enabled large-scale heterogeneous Lattice Boltzmann multiphase flow simulations 17

OpenMP4.5-enabled large-scale heterogeneous Lattice Boltzman...

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作者： Xu, Chuanfu Wang, Xi Che, Yonggang Wang, Zhenghua Li, Dali Natl Univ Def Technol Coll Comp Changsha Peoples R China Natl Univ Def Technol Coll Aeronaut & Astronaut Changsha Peoples R China

ISBN: (纸本)9781728143286

Modern heterogeneous high-end computing systems featuring many-core co-processors/accelerators pose tough challenges to parallelize and optimize real-world scientific codes. In this paper, we demonstrate highly scalable 3D Lattice Boltzmann multiphase flow simulations on the heterogeneous Tianhe-2 supercomputer using MPI+OpenMP+SIMD. We highlight the use of the OpenMP4.5 accelerator programming model to collaborate CPUs and Intel Many Integrated Cores (MIC) co-processors, and present a range of optimizations to exploit hierarchical parallelism on the heterogeneous architecture. With SIMD-friendly data structures, computation reordering, cache blocking and auto-vectorization, we dramatically optimize the single-thread performance for typical LBM computational kernels on a CPU and MIC core. After implementation of shared-memory OpenMP threading, we further improve the OpenMP performance by enabling huge paging and OpenMP collapse clause on the thread-rich MIC architecture. To enhance the collaborative efficiency among intra-node CPUs and co-processors, we propose a flexible load balance model with heterogeneous domain decomposition for CPU-MIC task allocation, as well as asynchronous offloading to overlap operations of CPUs and multiple MICs. We effectively overlap all levels of CPU-MIC computation/communication and minimize the cost of halo exchanges as far as possible in large-scale scenario. 3D liquid and gases multi-phase cases simulating drop impact with gravity effect using D3Q19 Lattice Boltzmann discretization and Shan-Chen BGK collision model are presented, achieving a weak parallel efficiency of above 80% in going from 128 to 2048 compute nodes.

关键词： heterogeneous parallel computing lattice Boltzmann methods many-core processor OpenMP4.5 accelerator programming model

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Decentralized Storage System for Edge Computing 18

Decentralized Storage System for Edge Computing

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18th international symposium on parallel and distributed Computing (ISPDC)

作者： Gheorghe, Alin-Gabriel Crecana, Constantin-Cosmin Negru, Catalin Pop, Florin Dobre, Ciprian Univ Politehn Bucuresti Fac Automat Control & Comp Bucharest Romania Natl Inst Res & Dev Informat ICI Bucharest Romania

ISBN: (纸本)9781728138015

With the increases in mobile usage, data sensors and IoT devices the classical Cloud approach encounters a lot of problems in network congestion and in the response speed. A method for optimizing the communication between the devices and the cloud is to place the computing power in the proximity of sources. Edge Computing is a paradigm that proposes data processing and storage at the edge of the network. For the Mobile Edge Computing, the edge is represented by pervasive Radio Access Networks. Edge computing addresses a variety of applications and use cases. For instance, edge model can be used in Smart Cities, Cyber-physical infrastructures, Wireless Sensors and Actuators Networks. In this model, the tasks and the data are submitted first on the gateway nodes, which are devices with computation and storage capabilities. In this way the latency is minimized, and the network bandwidth is preserved. In this paper we design and evaluate a novel decentralized storage system for Edge Computing, aiming to provide a unified storage for data generated by different edge devices.

关键词： Storage Edge Computing decentralized distributed system

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A Study of Graph Analytics for Massive Datasets on distributed Multi-GPUs

A Study of Graph Analytics for Massive Datasets on Distribut...

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international symposium on parallel and distributed processing (IPDPS)

作者： Vishwesh Jatala Roshan Dathathri Gurbinder Gill Loc Hoang V. Krishna Nandivada Keshav Pingali The University of Texas at Austin Austin Texas USA IIT Madras Chennai Tamil Nadu India

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

There are relatively few studies of distributed GPU graph analytics systems in the literature and they are limited in scope since they deal with small data-sets, consider only a few applications, and do not consider the interplay between partitioning policies and optimizations for computation and *** this paper, we present the first detailed analysis of graph analytics applications for massive real-world datasets on a distributed multi-GPU platform and the first analysis of strong scaling of smaller real-world datasets. We use D-IrGL, the state-of-the-art distributed GPU graph analytical framework, in our study. Our evaluation shows that (1) the Cartesian vertex-cut partitioning policy is critical to scale computation out on GPUs even at a small scale, (2) static load imbalance is a key factor in performance since memory is limited on GPUs, (3) device-host communication is a significant portion of execution time and should be optimized to gain performance, and (4) asynchronous execution is not always better than bulk-synchronous execution.

关键词： Graphics processing units Performance evaluation Optimization Computer architecture Mirrors Synchronization Computational modeling

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