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检索条件"任意字段=2nd International Symposium on Parallel and Distributed Processing and Applications"

共 1711 条记录，以下是281-290 订阅

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Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-based Multicores Executing parallel Data Analytics applications 32

Software-Hardware Managed Last-level Cache Allocation Scheme...

引用

27th international Heterogeneity in Computing Workshop in conjunction with 32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Ahmad, Masab Dogan, Halit Checconi, Fabio Que, Xinyu Buono, Daniele Khan, Omer Univ Connecticut Storrs CT 06269 USA IBM Res Yorktown Hts NY 10598 USA

ISBN: (纸本)9781538643686

Developments in machine learning and graph analytics have seen these fields establish themselves as pervasive in a wide range of applications. Non-volatile memory (NVRAM) offers higher capacity and information retainment in case of power loss, therefore it is expected to be adopted for such applications. However, the asymmetric access latencies of NVRAM greatly degrade performance. The focus of this paper is to reduce the effect of memory access latency on emerging machine learning and graph workloads. The proposed mechanism uses software tagging of application data structures so as to control on-chip cache evictions based on data type and reuse patterns in an NVRAM based multicore system. Learner models are developed that are capable of predicting cache allocations for a variety of machine learning and graph applications. The optimized learning model yields an average performance benefit of 21% compared to a system that does not optimize for the write latency challenges in NVRAM.

关键词： Random access memory Nonvolatile memory Software Resource management Data structures Hardware Multicore processing"

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GraphQ: Scalable PIM-Based Graph processing 52

GraphQ: Scalable PIM-Based Graph Processing

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52nd Annual IEEE/ACM international symposium on Microarchitecture (MICRO)

作者： Zhuo, Youwei Wang, Chao Zhang, Mingxing Wang, Rui Niu, Dimin Wang, Yanzhi Qian, Xuehai Univ Southern Calif Los Angeles CA 90007 USA Tsinghua Univ Beijing Peoples R China Beihang Univ Beijing Peoples R China Alibaba Inc Sunnyvale CA USA Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781450369381

processing-In-Memory (PIM) architectures based on recent technology advances (e.g., Hybrid Memory Cube) demonstrate great potential for graph processing. However, existing solutions did not address the key challenge of graph processing-irregular data movements. This paper proposes GraphQ, an improved PIM-based graph processing architecture over recent architecture Tesseract, that fundamentally eliminates irregular data movements. GraphQ is inspired by ideas from distributed graph processing and irregular applications to enable static and structured communication with runtime and architecture co-design. Specifically, GraphQ realizes: 1) batched and overlapped inter-cube communication by reordering vertex processing order;2) streamlined inter-cube communication by using heterogeneous cores for different access types. Moreover, to tackle the discrepancy between inter-cube and inter-node bandwidth, we propose a hybrid execution model that performs additional local computation during the inter-node communication. This model is general enough and applicable to asynchronous iterative algorithms that can tolerate bounded stale values. Putting all together, GraphQ simultaneously maximizes intra-cube, inter-cube, and internode communication throughput. In a zSim-based simulator with five real-world graphs and four algorithms, GraphQ achieves on average 3.3x and maximum 13.9x speedup, 81% energy saving compared with Tesseract. We show that increasing memory size in PIM also proportionally increases compute capability: a 4-node GraphQ achieves 98.34x speedup compared with a single node with the same memory size and conventional memory hierarchy.

关键词： graph analytics data movement memory systems 3D-stacked memory processing-in-memory near-data processing

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Performance optimization of fully anisotropic elastic wave propagation on 2nd Generation Intel® Xeon Phi™ processors 32

Performance optimization of fully anisotropic elastic wave p...

引用

32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Farres, Albert Rosas, Claudia Hanzich, Mauricio Duran, Alejandro Yount, Charles Univ Politecn Cataluna Barcelona Spain Barcelona Supercomp Ctr Barcelona Spain Intel Corp Iberia Madrid Spain Intel Corp Santa Clara CA USA

ISBN: (纸本)9781538655559

Improving the performance of stencil computations is a long-standing optimization challenge due to their inherent heavy memory-access patterns. This problem has been explored in many wave-propagation simulation engines. Moving towards implementations with elastic waves instead of acoustic ones (e.g., used in medical imaging) results in computationally more expensive processes along with increased memory usage. Despite the computational demand, the elevated cost of exploration combined the need for higher success rates is driving the oil & gas industry to adopt elastic anisotropic wave-propagation models as the core of many geophysical imaging mechanisms to extract subsurface features more accurately, increasing return on investment. To reduce time-to-solution, the more complex stencil codes must run efficiently on modern CPU architectures. The Intel Xeon Phi processors emerge as an energy-efficient solution that provides a good trade-off between market price and computing capability. In this paper, we study the effect of several optimization techniques using the YASK stencil-generation framework to implement and evaluate a 25-point stencil of an elastic-wave propagation engine for Intel Xeon Phi processors. The results showed improvements of up to 7x in computations and 8x in memory bandwidth with respect to the non-tuned version, reaching up to 75% of the attainable floating-point performance at the given operational intensity. We collected performance metrics for a set of the most representative optimizations and revealed the relation between each strategy and fundamental characteristics of both code and hardware.

关键词： Stencil-based wave propagation Performance optimizations Intel Xeon Phi Fully Staggered Grid

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Barrier Synchronization: Simplified, Generalized, and Solved without Mutual Exclusion 32

Barrier Synchronization: Simplified, Generalized, and Solved...

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Aravind, Alex Univ Northern British Columbia Dept Comp Sci Prince George BC Canada

ISBN: (纸本)9781538655559

Barrier synchronization is a fundamental concurrency issue encountered in a large number of concurrent and parallel applications that involve parallel processes cooperatively solving complex problems. Barrier synchronization essentially forces these parallel processes to wait until each one of them has reached a certain point in execution. Therefore, barrier synchronization has been considered as an inevitable synchronization construct for most parallel applications. Hence barrier synchronization or its variant has become an integral component of the most widely used parallel programming models such as OpenMP, MPI, MapReduce, and the bulk synchronous parallel (BSP) models. In [2], the authors stated that the performance of BSP model depends on 4 parameters the number of nodes, the speed of each node, the communication cost, and the synchronization cost. Among these, the synchronization cost is considered critical in improving the performance of any BSP implementation [2]. From parallel algorithm design and implementation perspective, we consider that the synchronization component is the most important one and its cost is the most critical performance factor for almost all the parallel programming models including BSP. This paper presents a class of simple barrier synchronization algorithms for shared memory systems. It includes general, efficient, and universal algorithms that are appealing from both practical and theoretical point of view. The correctness of the algorithms are proved. The algorithms are briefly analyzed to expose their strengths and weaknesses.

关键词： Barrier synchronization Mapreduce BSP parallel and distributed computational models Concurrent programming parallel processing distributed computing

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Unobtrusive Asynchronous Exception Handling with Standard Java Try/Catch Blocks 32

Unobtrusive Asynchronous Exception Handling with Standard Ja...

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Mehrabi, Mostafa Giacaman, Nasser Sinnen, Oliver Univ Auckland Dept Elect & Comp Engn Parallel & Reconfigurable Comp Lab Auckland New Zealand

ISBN: (纸本)9781538643686

The sophisticated nature of parallel computing concepts makes parallel programming challenging. This has encouraged higher-level frameworks that conceal much of the complications behind abstraction layers. Paradigms in this category are mostly performance centric, and do not share the same sentiments for the robustness of asynchronous executions. This is while current applications demand consistency in addition to fast performance. Therefore, programming environments that offer high-level support for asynchronous exception handling will have higher chances for popularity. This paper discusses our latest enhancements to @PT, a parallel programming environment that is based on Java annotations. The proposed concept promotes the robustness of parallelized programs by adhering to the familiar exception handling standards of sequential code, and reducing the asynchronous execution concerns at the API level. This study suggests that the concept simplifies efficient management of asynchronous exceptions, which appears to be a challenge in parallel programming.

关键词： parallel programming exception handling asynchronous annotations @PT

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Large Bandwidth-Efficient FFTs on Multicore and Multi-Socket Systems 32

Large Bandwidth-Efficient FFTs on Multicore and Multi-Socket...

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Popovici, Doru Thom Low, Tze Meng Franchetti, Franz Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

ISBN: (纸本)9781538643686

Current microprocessor trends show a steady increase in the number of cores and/or threads present on the same CPU die. While this increase improves performance for compute-bound applications, the benefits for memory-bound applications are limited. The discrete Fourier transform (DFT) is an example of such a memory-bound application, where increasing the number of cores does not yield a corresponding increase in performance. In this paper, we present an alternate solution for using the increased number of cores/threads available on a typical multicore system. We propose to repurpose some of the cores/threads as soft Direct Memory Access (DMA) engines so that data is moved on and off chip while computation is performed. Overlapping memory accesses with computation permits us to preload and reshape data so that computation is more efficient. We show that despite using fewer cores/threads for computation, our approach improves performance relative to MKL and FFTW by 1.2x to 3x for large multi-dimensional DFTs of up to 2048(3) on one and two-socket Intel and AMD systems.

关键词： Discrete Fourier transforms Instruction sets Multicore processing Three-dimensional displays Matrix decomposition Memory management"

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Quantifying the Performance and Energy-Efficiency Impact of Hardware Transactional Memory on Scientific applications on Large-Scale NUMA Systems 32

Quantifying the Performance and Energy-Efficiency Impact of ...

引用

32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Park, Jinsu Baek, Woongki UNIST Sch ECE Ulsan South Korea

ISBN: (纸本)9781538643686

Hardware transactional memory (HTM) is supported by widely-used commodity processors. While the effectiveness of HTM has been evaluated based on small-scale multi-core systems, it still remains unexplored to quantify the performance and energy-efficiency of HTM for scientific workloads on large-scale NUMA systems, which have been increasingly adopted to high-performance computing. To bridge this gap, this work investigates the performance and energy-efficiency impact of HTM on scientific applications on large-scale NUMA systems. We first quantify the performance and energy efficiency of HTM for scientific workloads based on the widely-used CLOMP-TM benchmark. We then discuss a set of generic software optimizations that can be effectively used to improve the performance and energy efficiency of transactional scientific workloads on large-scale NUMA systems. Finally, we present case studies in which we apply a set of the optimizations to representative transactional scientific applications and significantly optimize their performance and energy efficiency on large-scale NUMA systems.

关键词： Benchmark testing Synchronization Program processors Hardware Optimization Genomics"

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Predictable Efficiency for Reconfiguration of Service-Oriented Systems with Concerto

Predictable Efficiency for Reconfiguration of Service-Orient...

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： Maverick Chardet Hélène Coullon Christian Perez Inria LS2N UBL IMT Atlantique Nantes France Inria CNRS ENS de Lyon UCBL LIP Univ. Lyon Lyon Cedex 07 France

ISBN: (数字)9781728160955

ISBN: (纸本)9781728196497

Dynamic reconfiguration of distributed software systems is nowadays gaining interest because of the emergence of dynamic IoT and smart applications as well as large scale dynamic infrastructures (e.g., Fog and Edge computing). When quality of service and experience is of prime importance, efficient reconfiguration is necessary, as well as performance predictability to decide when a reconfiguration should occur. This paper tackles the problem of efficient execution of a reconfiguration plan and its predictability with Concerto, a reconfiguration model supporting a high level of parallelism. Evaluation performed on synthetic cases and on two real production scenarios show that Concerto provides better performance than state-of- the-art systems with accurate time estimation.

关键词： parallel processing Tools Servers Software systems Estimation Planning

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Efficient Gradient Boosted Decision Tree Training on GPUs 32

Efficient Gradient Boosted Decision Tree Training on GPUs

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27th international Heterogeneity in Computing Workshop in conjunction with 32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Wen, Zeyi He, Bingsheng Ramamohanarao, Kotagiri Lu, Shengliang Shi, Jiashuai Natl Univ Singapore Singapore Singapore Univ Melbourne Melbourne Vic Australia South China Univ Technol Guangzhou Guangdong Peoples R China

ISBN: (纸本)9781538643686

In this paper, we present a novel parallel implementation for training Gradient Boosting Decision Trees (GBDTs) on Graphics processing Units (GPUs). Thanks to the wide use of the open sourced XGBoost library, GBDTs have become very popular in recent years and won many awards in machine learning and data mining competitions. Although GPUs have demonstrated their success in accelerating many machine learning applications, there are a series of key challenges of developing a GPU-based GBDT algorithm, including irregular memory accesses, many small sorting operations and varying data parallel granularities in tree construction. To tackle these challenges on GPUs, we propose various novel techniques (including Run-length Encoding compression and thread/ block workload dynamic allocation, and reusing intermediate training results for efficient gradient computation). Our experimental results show that our algorithm named GPU-GBDT is often 10 to 20 times faster than the sequential version of XGBoost, and achieves 1.5 to 2 times speedup over a 40 threaded XGBoost running on a relatively high-end workstation of 20 CPU cores. Moreover, GPU-GBDT outperforms its CPU counterpart by 2 to 3 times in terms of performance-price ratio.

关键词： Training Graphics processing units parallel processing Decision trees Instruction sets Machine learning algorithms Machine learning"

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Building a Cloud-Ready Program: A highly scalable Implementation based on Kubernetes 18

Building a Cloud-Ready Program: A highly scalable Implementa...

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2nd international Conference on Advances in Image processing (ICAIP) / 2nd international Conference on Software Engineering and Development (ICSED

作者： Li, Qiankun Yin, Gang Wang, Tao Yu, Yue Natl Univ Def Technol Natl Lab Parallel & Distributed Proc Changsha 410073 Peoples R China

ISBN: (纸本)9781450364607

Build system, which can convert source codes into applications, is essential for the development of software. The general build systems that relying on single physical or cloud host to run bring problems such as system security, resource shortage, overload, and low availability in the face of massive build requests. After modularizing and streamlining the steps during a build process, this paper proposes a system that introduces container technology and then builds a large-scale, real-time, and huge-concurrency supported build system based on Kubernetes[1]. The system provides a highly scalable and feature-stable cloud architecture that supports huge concurrency with lower resource consumption. Also, the system controls programs' behaviors very well to avoid potential security and resource issues and shows excellent performance in concurrency, scalability, security, and load balance even when handling a large number of build tasks.

关键词： Build system Container Kubernetes Concurrent build

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