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检索条件"任意字段=2nd International Symposium on Parallel and Distributed Processing and Applications"

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V2V: Vector Embedding of a Graph and applications 32

V2V: Vector Embedding of a Graph and Applications

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27th international Heterogeneity in Computing Workshop in conjunction with 32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Trong Duc Nguyen Tirthapura, Srikanta Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

ISBN: (纸本)9781538655559

We present V2V, a method for embedding each vertex in a graph as a vector in a fixed dimensional space. Inspired by methods for word embedding such as word2vec, a vertex embedding is computed through enumerating random walks in the graph, and using the resulting vertex sequences to provide the context for each vertex. This embedding allows one to use well-developed techniques from machine learning to solve graph problems such as community detection, graph visualization, and vertex label prediction. We evaluate embeddings produced by V2V through comparing results obtained using V2V with results obtained through a direct application of a graph algorithm, for community detection. Our results show that. V2V provides interesting trade-offs among computation time and accuracy.

关键词： Data visualization Clustering algorithms Machine learning Machine learning algorithms Approximation algorithms Neural networks Training"

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Unobtrusive Support for Asynchronous GUI Operations with Java Annotations 32

Unobtrusive Support for Asynchronous GUI Operations with Jav...

引用

32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Mehrabi, Mostafa Giacaman, Nasser Sinnen, Oliver Univ Auckland Dept Elect & Comp Engn Parallel & Reconfigurable Comp Lab Auckland New Zealand

ISBN: (纸本)9781538655559

The complexities involved in parallel programming encourage frameworks to detach programmers from these concerns via higher-level abstraction. The high-performance nature of parallel computing drifts the focus of these programming environments towards facilitating and safeguarding faster computations. Therefore, aspects such as asynchronous graphical user interfaces (GUIs) do not see as much emphasis, even though many applications today depend on concurrent human-computer interactions. The significance of this topic is growing such that facilitating the efficient management of asynchronous GUI operations is currently a virtue, but will soon become necessary for parallel-programming frameworks. This paper discusses an unobtrusive and annotation-based approach for managing different types of asynchronous GUI operations within the layout of familiar sequential code. The proposed solution minimizes the restructuring of sequential code, in order to simplify developing, testing and maintaining GUI-based applications. Furthermore, the paper presents an implementation of the concept for @PT, a parallel programming environment based on Java annotations. The evaluation discussed in this paper suggests that the proposed mechanism is valid, and demonstrates timely and efficient handling of asynchronous GUI operations.

关键词： parallel programming asynchronous GUI responsiveness Java annotations @PT

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Joint Server and Network Energy Saving in Data Centers for Latency-Sensitive applications 32

Joint Server and Network Energy Saving in Data Centers for L...

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Zhou, Liang Chou, Chih-Hsun Bhuyan, Laxmi N. Ramakrishnan, K. K. Wong, Daniel Univ Calif Riverside Comp Sci & Engn Dept Riverside CA 92521 USA Univ Calif Riverside Elect & Comp Engn Dept Riverside CA 92521 USA

ISBN: (纸本)9781538643686

Achieving energy proportionality in data centers supporting latency-sensitive applications is challenging because of the strict Service Level Agreements. Previous works individually focus on making the server energy proportional or reducing the data center network's power consumption for latency-tolerant applications. In this paper, we propose EPRONS to minimize the overall data center's power consumption with latency-sensitive applications by trading-off network slack in favor of providing additional slack for computations. We utilize the linear programming model to consolidate latency-sensitive search queries and latency-tolerant background flows to a minimal subnet of the topology by turning off unused switches and links without violating the application deadlines. Servers take advantage of the additional 'network-provided' slack to allow slowing down request processing. For servers, we design a novel power saving technique using Dynamic Voltage and Frequency Scaling (DVFS) based on the average tail latency of a request. If needed, we turn on a minimal number of additional network links and switches to reduce network latency while still maximizing entire data center's power saving. Experimental results show that our scheme saves up to 31.25% of a data center's total power budget.

关键词： Data Center Latency-Sensitive Energy Proportional DVFS Traffic Consolidation

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Approximation algorithm for scheduling applications on hybrid multi-core machines with communications delays 32

Approximation algorithm for scheduling applications on hybri...

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Aba, Massinissa Ait Zaourar, Lilia Munier-Kordon, Alix CEA LIST Comp & Design Environm Lab F-91191 Gif Sur Yvette France LIP6 UPMC 4 Pl Jussieu F-75005 Paris France

ISBN: (纸本)9781538655559

This paper presents an efficient algorithm with performance guarantee (approximation algorithm) to solve task scheduling problem on hybrid platform. The underlying platform architecture in this work is composed by two types of resources CPU and GPU, often called hybrid parallel multi-core platforms. We consider here for each type of resource identical nodes with communications delays. We focus in finding a generic approach to schedule applications presented by DAG (Directed Acyclic Graph) that minimizes makespan by considering communication delay between processors and tasks. A 6-approximation scheduling algorithm is proposed and evaluated in comparison to exact solutions and to another method. We demonstrate that the proposed algorithm achieves a close-to-optimal performance. Finally, our algorithm has been experimented on a large number of instances. These tests assess the good practical behavior of the algorithms with respect to the state-of-the-art solutions whenever these exist.

关键词： DAG applications makespan hybrid CPU GPU approximation algorithm scheduling

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MIDAS: Multilinear Detection at Scale 32

MIDAS: Multilinear Detection at Scale

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Ekanayake, Saliya Cadena, Jose Wickramasinghe, Udayanga Vullikanti, Anil Kumar Virginia Tech Network Dynam & Simulat Sci Lab Blacksburg VA 24061 USA Indiana Univ Dept Comp Sci Bloomington IN 47405 USA

ISBN: (纸本)9781538643686

We focus on two classes of problems in graph mining: (1) finding trees and (2) anomaly detection in complex networks using scan statistics. These are fundamental problems in a broad class of applications. Most of the parallel algorithms for such problems are either based on heuristics, which do not scale very well, or use techniques like color coding, which have a high memory overhead. In this paper, we develop a novel approach for parallelizing both these classes of problems, using an algebraic representation of subgraphs as monomials-this methodology involves detecting multilinear terms in multivariate polynomials. Our algorithms show good scaling over a large regime, and they run on networks with close to half one billion edges. The resulting parallel algorithm for trees is able to scale to subgraphs of size 18, which has not been done before, and it significantly outperforms the best prior color coding based method (FASCIA) by more than two orders of magnitude. Our algorithm for network scan statistics is the first such parallelization, and it is able to handle a broad class of scan statistics functions with the same approach.

关键词： Encoding Algebra Image color analysis Anomaly detection parallel algorithms Fascia Optimization"

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Optimizing parallel Graph Connectivity Computation via Subgraph Sampling 32

Optimizing Parallel Graph Connectivity Computation via Subgr...

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27th international Heterogeneity in Computing Workshop in conjunction with 32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Sutton, Michael Ben-Nun, Tal Barak, Amnon Hebrew Univ Jerusalem Dept Comp Sci IL-91904 Jerusalem Israel Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9781538643686

Connected component identification is a fundamental problem in graph analytics, serving as a basis for subsequent computations in a wide range of applications. To determine connectivity, several parallel algorithms, whose complexity is proportional to the number of edges or graph diameter, have been proposed. However, an optimal algorithm may extract graph components by working proportionally to the number of vertices, which can be orders of magnitude lower than the number of edges. We propose Afforest: an extension of the Shiloach-Vishkin connected components algorithm that approaches optimal work efficiency by processing subgraphs in each iteration. We prove the convergence of the algorithm, analyze its work efficiency characteristics, and provide further techniques to speed up processing graphs containing a huge component. Designed with modern parallel architectures in mind, we show that the algorithm exhibits higher memory locality than existing methods. Using both synthetic and real-world graphs, we demonstrate that Afforest achieves speedups of up to 67x over the state-of-the-art on multi-core CPUs (Broadwell, POWER8) and up to 23x on GPUs (Pascal).

关键词： Connected Components parallel Algorithms Graph Algorithms

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Exploration and Design of a Synchronous Message Passing Framework for a CPU-NPU Heterogeneous Architecture 32

Exploration and Design of a Synchronous Message Passing Fram...

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Pennefather, Sean Bradshaw, Karen Irwin, Barry Rhodes Univ Dept Comp Sci Grahamstown South Africa

ISBN: (纸本)9781538655559

In this paper we present the development of a framework for communication between an NPU (network processing unit) and CPU through synchronous message passing that is compliant with the synchronous communication events of the CSP formalisms. This framework is designed to be used for passing generic information between application components operating on both architectures and is intended to operate in conjunction with existing datapaths present on the NPU which in turn are responsible for network traffic transmission. An investigation of different message passing topologies is covered before the proposed message passing fabric is presented. As a proof of concept, an initial implementation of the fabric is developed and tested to determine its viability and correctness. Through testing it is shown that the implemented framework operates as intended. However, it is noted the throughput of the exploratory implementation is not considered suitable for high-performance applications and further evaluation is required.

关键词： Heterogeneous Architectures parallel Computing Network Flow Processors

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OO-VR: NUMA Friendly Object-Oriented VR Rendering Framework For Future NUMA-Based Multi-GPU Systems 19

OO-VR: NUMA Friendly Object-Oriented VR Rendering Framework ...

引用

46th international symposium on Computer Architecture (ISCA)

作者： Xie, Chenhao Xin, Fu Chen, Mingsong Song, Shuaiwen Leon Pacific Northwest Natl Lab Richland WA 99352 USA Univ Houston Houston TX 77004 USA Univ Houston ECE Dept ECMOS Lab Houston TX 77004 USA East China Normal Univ Sch Comp Sci & Software Engn Shanghai Peoples R China Univ Sydney Sydney NSW Australia

ISBN: (纸本)9781450366694

With the strong computation capability, NUMA-based multi-GPU system is a promising candidate to provide sustainable and scalable performance for Virtual Reality (VR) applications and deliver the excellent user experience. However, the entire multi-GPU system is viewed as a single GPU under the single programming model which greatly ignores the data locality among VR rendering tasks during the workload distribution, leading to tremendous remote memory accesses among GPU models (GPMs). The limited inter- GPM link bandwidth (e.g., 64GB/s for NVlink) becomes the major obstacle when executing VR applications in the multi-GPU system. By conducting comprehensive characterizations on different kinds of parallel rendering frameworks, we observe that distributing the rendering object along with its required data per GPM can reduce the inter-GPM memory accesses. However, this object-level rendering still faces two major challenges in NUMA-based multi- GPU system: (1) the large data locality between the left and right views of the same object and the data sharing among different objects and (2) the unbalanced workloads induced by the software- level distribution and composition mechanisms. To tackle these challenges, we propose object-oriented VR rendering framework (OO-VR) that conducts the software and hardware co-optimization to provide a NUMA friendly solution for VR multi-view rendering in NUMA-based multi-GPU systems. We first propose an object-oriented VR programming model to exploit the data sharing between two views of the same object and group objects into batches based on their texture sharing levels. Then, we design an object aware runtime batch distribution engine and distributed hardware composition unit to achieve the balanced workloads among GPMs and further improve the performance of VR rendering. Finally, evaluations on our VR featured simulator show that OO-VR provides 1.58x overall performance improvement and 76% inter-GPM memory traffic reduction over the s

关键词： graphics processing units multiprocessing systems object-oriented programming parallel processing rendering (computer graphics) virtual reality Variable reluctance Multiprocessing systems object oriented programming Rendering Graphics processing Unit locality data virtual reality parallel processing (COMPUTERS) Rendering (computer graphics) Nonunified memory architecture Remote Memory object orientation

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CompStor: An In-Storage Computation Platform for Scalable distributed processing 32

CompStor: An In-Storage Computation Platform for Scalable Di...

引用

32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Torabzadehkashi, Mahdi Rezaei, Siavash Alves, Vladimir Bagherzadeh, Nader Univ Calif Irvine EECS Dept Irvine CA 92697 USA Univ Calif Irvine ICS Dept Irvine CA 92697 USA NGD Syst Inc Irvine CA USA

ISBN: (纸本)9781538655559

The explosion of data-centric and data dependent applications requires new storage devices, interfaces, and software stacks. Big data analytics solutions such as Hadoop, MapReduce and Spark have addressed the performance challenge by using a distributed architecture based on a new paradigm that relies on moving computation closer to data. In this paper, we describe a novel approach aimed at pushing the "move computation to data" paradigm to its ultimate limit by enabling highly efficient and flexible in-storage processing capability in solid state drives (SSDs). We have designed CompStor, an FPGA-based SSD that implement computational storage through a software stack (devices, protocol, interface, software, and systems) and a dedicated hardware for in-storage processing including a quadcore ARM processor subsystem. The dedicated hardware resources provide in-storage data analytics capability without degrading the performance of common storage device functions such as read, write and trim. Experimental results show up to 3X energy saving for some applications in comparison to the host CPU. To the best of our knowledge, the 24TB CompStor SSD is the first one capable of supporting in-storage computation running an operating system, enabling all types of applications and Linux shell commands to be executed in-place with no modification.

关键词： near data processing in-storage computing in-situ processing distributed processing non-volatile memory SSD direct-attached storage

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Performance Isolation of Data-Intensive Scale-out applications in a Multi-tenant Cloud 32

Performance Isolation of Data-Intensive Scale-out Applicatio...

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32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Lama, Palden Wang, Shaoqi Zhou, Xiaobo Cheng, Dazhao Univ Texas San Antonio Dept Comp Sci San Antonio TX 78249 USA Univ Colorado Dept Comp Sci Colorado Springs CO 80907 USA Univ N Carolina Dept Comp Sci Charlotte NC USA

ISBN: (纸本)9781538643686

Data-intensive applications often suffer from performance variability and degradation in the cloud due to intrinsically complex problem of performance interference that arises from multi-tenancy. Although application-level approach of straggler mitigation for scale-out data processing frameworks such as MapReduce and Spark, address the issue to some extent, they incur extra resource and often react after tasks have already slowed down. In this paper, we present PerfCloud, a novel system software that utilizes system level performance metrics for early detection of performance interference in a multi-tenant cloud, and provides non-invasive performance isolation through fine-grained resource control. Unlike existing works, PerfCloud does not require time-consuming workload profiling, or intrusive modification of the application framework and the operating system. We implemented PerfCloud on NSF Cloud's Chameleon testbed using KVM for virtualization, and OpenStack for cloud management. Experimental results with Hadoop MapReduce and Spark benchmarks show that PerfCloud effectively reduces their job completion time, decreases performance variability, and improves resource utilization efficiency while minimizing the performance degradation of other colocated VMs.

关键词： performance isolation resource scheduling cloud

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