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Energy-efficient strategy for placement of online services on dynamic availability resources in volunteer Cloud 16

Energy-efficient strategy for placement of online services o...

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Ben Maaouia, Omar Cerin, Christophe Fkaier, Hazem Jemni, Mohamed Univ Tunis El Manar Univ Tunis ENSIT LATICEFST Campus 2092 Manar 2 Tunis Tunisia Univ Paris 13 CNRS UMR 7030 LIPN Villetaneuse France Univ Tunis ENSIT LATICE Tunis Tunisia

ISBN: (纸本)9781728111414

Cloud computing is regarded as the best generation of computation that relies on shared computing resources rather than having local servers or personal devices to handle different applications. Knowing that, from one side, computing resources can be dynamically allocated according to consumer requirements and from the other side, virtual machine deployment preferences has an important role in Cloud computing for improving resource use. In this paper, we propose an online placement strategy of services on dynamic availability resources in order to reduce energy consumption. Dynamic deployment of services is a key issue of Cloud computing;there are still many areas to be studied, especially for dynamic environments. Unlike the infrastructure topology of the traditional Clouds, i.e. the data centers to which users are connected, in the volunteer Cloud, users and data centers can process multiple requests. Indeed, the volunteer nodes are useful for the Cloud elasticity. However, they are not usually available. The dynamic availability is one of the biggest concerns for the consumers. In addition, live migration of services is a widely used technique for dynamically allocating resources in a volunteer Cloud to overcome such issue. In this work, we investigate the problem of energy efficient online task allocation in volunteer Cloud environment, where the dynamic services can be allocated to a set of dynamic availability resources. We propose through this paper an online heuristic called Dynamic Shortest Path Strategy (DSPS) in order to generate a good planning that minimizes the energy consumption of applications. Our contribution respects various constraints such as availability, capacity of machines and duplications factor of applications. A series of experiments are illustrated to validate the potential of our approach.

关键词： Allocation Dynamic services Dynamic availability resources Online placement Minimization of energy consumption Volunteer Cloud

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Optimizing tiled matrix-matrix product according to cache performance enhancement 16

Optimizing tiled matrix-matrix product according to cache pe...

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Hammami, Emna Slama, Yosr Univ Tunis El Manar Fac Sci Tunis Campus 2092 Manar 2 Tunis Tunisia

ISBN: (纸本)9781728111414

Loop tiling is an important optimization technique to improve the practical performance of loop nests in terms of data locality. Thus, by reordering loop iterations, accesses to the closest data become within a relatively short timeframe. Nevertheless, the growing variation of tile sizes in a tiled code leads to significant difference in performance as well as completion time. Therefore, an effective selection of optimal tile sizes has become a critical challenge to tiled codes performance in front of the evolution of memory hierarchies in depth and complexity. Past works, which only target old platforms, have pursued two types of algorithms for tile size selection, i. e. analytical and empirical. However, following the recent processor's development, it becomes necessary to adapt such selections in a large space of tiled codes to the new architectures by taking into account the target hardware characteristics such as cache size, cache line size and set-associativity. It is in this context that this paper revisits the tile size selection problem for the matrix-matrix product (MMP) kernel. Indeed, we propose an analytical heuristic to choose optimal tile sizes for MMP aiming at increasing data reuse and reducing the completion time. Further, we carried out a series of experiments targeting a multicore machine to evaluate the interest of our approach, which improves measured execution time when compared to previous works.

关键词： Cache line Cache size Capacity misses Data reuse Interference misses Loop tiling Set-associativity Tile size

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Web Service Recommendation via Combining Doc2Vec-based Functionality Clustering and DeepFM-based Score Prediction 16

Web Service Recommendation via Combining Doc2Vec-based Funct...

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Zhang, Xiangping Liu, Jianxun Cao, Buqing Xiao, Qiaoxiang Wen, Yiping Hunan Univ Sci & Technol Key Lab Knowledge Proc & Networked Mfg Xiangtan Peoples R China

ISBN: (纸本)9781728111414

Due to the rapid growth in both the number and diversity of Web services on the Internet, it becomes increasingly difficult for developer to find the desired and appropriate Web services for Mashup creation. Even if the existing approaches show improvements in Web APIs recommendation, it is still challenging to recommend Web APIs with high accuracy and good diversity. Some of them integrate functionality clustering and the quality of service to recommend Web APIs for Mashup creation, but do not consider the high-order composition interaction relationship among functionality information, quality attributes. In this paper, we propose a novel Web APIs recommendation method via integrating the functionality clustering of service and the quality of service. In this method, it firstly obtains the functionality clustering by using Doc2Vec to cluster the description document of Web APIs. Then, the deep factorization machine model is used to extract the multi-dimension quality attributes of service and mine the high-order composition interaction relationship between them. Finally, the comparative experiments are performed on Programmable Web dataset and experimental results show that our method significantly improves the performance of Web API recommendation in term of precision, recall, purity, entropy, DCG and HMD.

关键词： Web API Recommendation Mashup Creation Document representation DeepFM QoS

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URL2Vec: URL Modeling with Character Embeddings for Fast and Accurate Phishing Website Detection 16

URL2Vec: URL Modeling with Character Embeddings for Fast and...

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Yuan, Huaping Yang, Zhenguo Chen, Xu Li, Yukun Liu, Wenyin Guangdong Univ Technol Web Ident Secur Lab Guangzhou Guangdong Peoples R China Guangdong Univ Technol Sch Comp Sci & Technol Guangzhou Guangdong Peoples R China Guangdong Univ Technol Sch Automat Guangzhou Guangdong Peoples R China City Univ Hong Kong Dept Comp Sci Hong Kong Peoples R China

ISBN: (纸本)9781728111414

A deep learning-based approach to phishing detection is proposed. Specifically, websites' URLs and the characters in these URLs are mapped to documents and words, respectively, in the context of word2vec-based word embedding learning. Consequently, character embedding can be achieved from a corpus of URLs in an unsupervised manner. Furthermore, we combine character embedding with the structures of URLs to obtain the vector representations of the URLs. In particular, an URL is partitioned into the following five sections: URL protocol, sub-domain name, domain name, domain suffix, and URL path. To identify the phishing URLs, existing classification algorithms can be used smoothly on the vector representations of the URLs, avoiding laborious work on designing effective features manually and empirically. For evaluations, we collect a large-scale dataset, i.e., 1 Million Phishing Detection Dataset (1M-PD), which has been released for public use. Extensive experiments conducted on two real-world datasets show the effectiveness of the proposed approach, which achieves an accuracy of 99.69% with 0.40% false positive and 99.79% true positives on the 1M-PD dataset. In particular, the proposed approach detects each URL in 32ms on average merely on a personal computer, which is much faster than existing approaches and even can be considered real-time.

关键词： Information Security Phishing Detection Deep Learning Character Embedding

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Classification of Textual Data in distributed Environment 2

Classification of Textual Data in Distributed Environment

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2nd international Conference on Advances in Computing, Control and Communication Technology (IAC3T)

作者： Gupta, Sonali Kumar, Vidit Pant, Bhaskar Graph Era Deemed Univ Comp Sci & Engn Dehra Dun Uttarakhand India

ISBN: (纸本)9781538641460

Nowadays data is generating at a very fast pace through internet usage and other sources in large volumes termed as Big Data. A large portion of generated data is in text form collected through emails, blogs, social networking sites, e-commerce reviews etc. which requires deep analysis to extract meaningful patterns from it for applications such as business decision making, social media monitoring, spam detection etc. This results in incapability for processing and storing this data. So it must be handled or processed using parallel computing tools and machine learning algorithms. In this work, we have used Naive Bayes classifier to classify textual data in Hadoop environment using Mahout. This experiment is carried out by using 20 news group dataset and achieved accuracy with 88.38%. After evaluating results we have found that when we increase the number of Hadoop clusters, the processing speed on clusters increase as Apache Hadoop can process large volume of datasets efficiently using map-reduce paradigm.

关键词： Hadoop Big Data Mahout Machine learning Naive Bayes

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OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator 24

OuterSPACE: An Outer Product based Sparse Matrix Multiplicat...

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24th IEEE international symposium on High Performance Computer Architecture (HPCA)

作者： Pal, Subhankar Beaumont, Jonathan Park, Dong-Hyeon Amarnath, Aporva Feng, Siying Chakrabarti, Chaitali Kim, Hun-Seok Blaauw, David Mudge, Trevor Dreslinski, Ronald Univ Michigan Ann Arbor MI 48109 USA Arizona State Univ Tempe AZ USA

ISBN: (纸本)9781538636596

Sparse matrices are widely used in graph and data analytics, machine learning, engineering and scientific applications. This paper describes and analyzes OuterSPACE, an accelerator targeted at applications that involve large sparse matrices. OuterSPACE is a highly-scalable, energy-efficient, reconfigurable design, consisting of massively parallel Single Program, Multiple Data (SPMD)style processing units, distributed memories, high-speed crossbars and High Bandwidth Memory (HBM). We identify redundant memory accesses to non-zeros as a key bottleneck in traditional sparse matrix-matrix multiplication algorithms. To ameliorate this, we implement an outer product based matrix multiplication technique that eliminates redundant accesses by decoupling multiplication from accumulation. We demonstrate that traditional architectures, due to limitations in their memory hierarchies and ability to harness parallelism in the algorithm, are unable to take advantage of this reduction without incurring significant overheads. OuterSPACE is designed to specifically overcome these challenges. We simulate the key components of our architecture using gem5 on a diverse set of matrices from the University of Florida's SuiteSparse collection and the Stanford Network Analysis Project and show a mean speedup of 7.9x over Intel Math Kernel Library on a Xeon CPU, 13.0x against cuSPARSE and 14.0x against CUSP when run on an NVIDIA K40 GPU, while achieving an average throughput of 2.9 GFLOPS within a 24 W power budget in an area of 87 mm2.

关键词： Sparse matrix processing application-specific hardware parallel computer architecture hardware-software codesign hardware accelerators

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A Design of a Programmable Impedance Scaling Circuit for Low Frequency applications

A Design of a Programmable Impedance Scaling Circuit for Low...

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2018 international symposium on Intelligent Signal processing and Communication Systems, ISPACS 2018

作者： Ohbuchi, Takeshi Fujishiro, Koutarou Matsumoto, Fujihiko National Defense Academy Department of Applied Physics 1-10-20 Hashirimizu Yokosuka239-8686 Japan

ISBN: (纸本)9781538657713

A large capacitor is needed for low-frequency active filters to process biomedical signals. The large capacitor is implemented by an impedance scaling circuit. However, the apparent capacitance of the conventional impedance scaling circuit cannot be tuned because that the scaling factor of the impedance scaling circuit is designed by the size of transistors of a negative current feedback circuit. This paper presents a digitally programmable impedance scaling circuit using electrical switches. The proposed circuit is realized by controlling the number of parallel MOS devices which compose the negative current feedback circuit using electrical switches. The validity of the proposed method is confirmed by simulations using HSPICE. The frequency characteristics of the proposed impedance scaling circuits using ideal switches are not deteriorated as compared with one of the conventional impedance scaling circuit. If the capacitor varies from -22% to +49.5%, the tuning error of the proposed impedance scaling circuit is within 0.5%. The proposed circuit can be applied to a 2nd order Butterworth filter whose cutoff frequency is 100 Hz. © 2018 IEEE.

关键词： Cutoff frequency

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Low Area & Memory Efficient VLSI Architecture Of 1D/2D DWT For Real Time Image Decomposition 8

Low Area & Memory Efficient VLSI Architecture Of 1D/2D DWT F...

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8th IEEE international symposium on Embedded Computing and System Design (ISED)

作者： Chakraborty, Anirban Banerjee, Ayan Indian Inst Engn Sci & Technol Dept Elect & Telecommun Engn Sibpur Howrah India

ISBN: (纸本)9781538665756

There is a dearth of high quality reconfigurable hardware for DWT which can be extensively used in various real time signal and image processing applications. In this article, we have focused on proposing a dedicated customizable hardware for DWT applicable to 1D/2D signal processing. We have proposed bit-serial distributed Arithmetic (DA) based VLSI architectures for 1D/2D DWT. Exploitation of DA enables us to make our designs Multiplierless, thereby consuming less area. Bit serial configuration of DA is also exploited to introduce modularity and pipelining in the proposed convolution DWT based 1D/2D architectures. Though the speed of the proposed designs may not be suitable for certain applications, a number of parallel channels can be introduced for the same. The provision of mode selection can efficiently be used to realize 9/7 and also 5/3 DWT filters in the same proposed architecture. In the proposed 1D/2D architecture, we have achieved about 50% memory size reduction, 30% reduction in area consumption and comparable speed in comparison to the other latest notable DWT architecture so far. We have verified the viability of our proposed 2D architecture by utilizing it in real time image decomposition.

关键词： DWT distributed arithmetic multiplierless image decomposition image enhancement

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Low-reliable low-latency networks optimized for HPC parallel applications 17

Low-reliable low-latency networks optimized for HPC parallel...

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17th IEEE international symposium on Network Computing and applications, NCA 2018

作者： Nguyen, Truong Thao Matsutani, Hiroki Koibuchi, Michihiro National Institute of Advanced Tsukuba Ibaraki305-8560 Japan Keio University 3-14-1 Hiyoshi Kohoku-ku Yokohama Kanagawa223-8522 Japan National Institute of Informatics 2-1-2 Hitotsubashi Chiyoda-ku Tokyo101-8430 Japan

ISBN: (纸本)9781538676592

High-end network standards, such as 400GbE, have been introduced Forwarding Error Correction (FEC) for maintaining the same bit error rate (BER) as that in traditional low-bandwidth interconnection networks. However, FEC operation latency overhead surprisingly becomes higher than the sum of all the other switch operation overheads, e.g., routing computation and switch allocation. FEC operation latency overhead significantly degrades the performance of parallel applications in HPC systems. Instead, in this study, we exploit the low-latency network design using a Hamming code that does not provide rigid error-free communication. Since it is consistent with existing frame format based on standard Reed-Solomon RS(544,514) with DC(64b/66b) direct linecode and TC(256b/257b) transcode, respectively, the influences upon the other network layer design are limited. Interestingly, a large number of parallel applications can accept the BER in such a Hamming code. Since lowering such a BER improves switch operation latency, the proposed network using the Hamming code improves the execution time of NAS parallel Benchmarks by 56% on average when compared to the counterpart RS-FEC networks. © 2018 IEEE.

关键词： Network layers

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distributed learning of process models for next activity prediction 18

Distributed learning of process models for next activity pre...

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22nd international Database Engineering and applications symposium, IDEAS 2018

作者： Ceci, Michelangelo Lanotte, Pasqua Fabiana Spagnoletta, Michele Malerba, Donato University of Bari Aldo Moro Italy CINI India University of Bari Aldo Moro Italy Exprivia S.p.A. Italy

ISBN: (纸本)9781450365277

Process mining is a research discipline that aims to discover, monitor and improve real processing using event logs. In this paper we tackle the problem of next activity prediction/recommendation via "nested prediction model" learning, that is, we first identify recurrent and frequent sequences of activities and then we learn a prediction model for each frequent sequence. The key principle underlying the design of the proposed solution is in the ability to process massive logs by means of a parallel and distributed solution (by exploiting the Spark parallel computation framework) which can make reasonable decisions in the absence of perfect models. Indeed, given the classical threshold for minimum support and a user-specified error bound, our approach exploits the Chernoff bound to mine "approximate" frequent sequences with statistical error guarantees on their actual supports. Experiments on real-world log data prove the effectiveness of the proposed approach. © 2018 Association for Computing Machinery.

关键词： Forecasting

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