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检索条件"任意字段=2nd International Symposium on Parallel and Distributed Processing and Applications"

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An Approach of Spatial Usage Optimization for NVM-based Storage System 15

An Approach of Spatial Usage Optimization for NVM-based Stor...

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15th IEEE international symposium on parallel and distributed processing with applications (ISPA) / 16th IEEE international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Zhang, Zheng Feng, Dan Tan, Zhipeng Chen, Jianxi Zhou, Wei Zhang, Jianquan Yang, Laurence T. Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Hubei Peoples R China Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan Hubei Peoples R China St Francis Xavier Univ Antigonish NS B2G 2W5 Canada Sci & Technol Commun Networks Lab Shijiazhuan Peoples R China

ISBN: (纸本)9781538637906

The emergency of non-volatile memory (NVM) can effectively address the performance gap between computing and storage due to its superior performance characteristics, including byte-addressability, low access latency and power consumption. However, NVM currently has high price and relative small capacity due to the process technology. In order to use the NVM in a cost-effective way, it is essential to improve the space utilization of NVM-based storage system. But, traditional file systems are not suitable for NVM as they are designed for block devices which incurs a large number of internal fragmentation and reduces the space utilization of storage system. On the other hand, the existing NVM-based file systems mostly focus on improving the system performance, failing to take full advantage of the byte-addressability of NVM. In this paper, we propose a Last Page Sharing (LPS) mechanism to improve the space utilization of NVM-based storage system. LPS utilizes the byteaddressability of NVM, and stores multiple small files or the tail data of files in the shared page together. We implement the Last Page Sharing scheme in an existing NVM-based file system and conduct several experiments to compare with other file systems to evaluate its efficiency. Experimental results show that, our approach reduces the space as much as 20% compared with Ext3, Ext4 and PMFS on average.

关键词： non-volatile memory file system internal fragmentation space utilization

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Understanding the Impact of Fine-Grained Data Sharing and Thread Communication on Heterogeneous Workload Development 16

Understanding the Impact of Fine-Grained Data Sharing and Th...

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16th international symposium on parallel and distributed Computing (ISPDC)

作者： Ta, Tuan Troendle, David Hu, Xiaoqi Jang, Byunghyun Univ Mississippi Dept Comp & Informat Sci University MS 38677 USA

ISBN: (纸本)9781538608623

The conventional OpenCL 1.x style CPU-GPU heterogeneous computing paradigm treats the CPU and GPU processors as loosely connected separate entities. At best each executes independent tasks, but, more commonly, the CPU idles while waiting for results from the GPU. No data-sharing and communications are allowed during kernel execution. This model limits the number of applications that can harness the tremendous computing power of two processors. OpenCL 2.x and compliant hardware introduce a new memory model that enables a new computing paradigm where the task-parallel CPU and data-parallel GPU are tightly coupled and can closely cooperate on shared data in a lock-based or non-blocking fashion. This new model maximizes hardware utilization and performance, and opens more applications to GPU acceleration. The most significant new OpenCL 2.x features are fine-grained data sharing and thread communication through shared virtual memory, CPU-GPU cache coherence support, and system-level atomics. However, few applications that can exploit the benefits of tightly coupled CPU-GPU heterogeneous processors have emerged. Programming and debugging in this new environment have proven challenging. The resulting lack of benchmark workloads have also left hardware architects uninformed. To facilitate truly heterogeneous workload development and hardware architecture research, this paper focuses on understanding the impact of fine-grained data sharing between the CPU and GPU for future heterogeneous workload development. To that goal, we identify three CPU-GPU cooperation paradigms, demonstrate their performance benefits on real hardware using both in-house and publicly available benchmarks, and profile their detailed behavior and characteristics using an architectural simulator. Our experiments demonstrate that truly heterogeneous implementations of our studied benchmarks outperform their corresponding conventional CPU or GPU versions by up to 59.5% and 36.6% respectively. We analyze

关键词： Graphics processing units Kernel Synchronization Instruction sets Hardware Benchmark testing

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Hardware efficient denoising system for real EOG signal processing

Hardware efficient denoising system for real EOG signal proc...

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2nd international symposium on Intelligent Systems Technologies and applications (ISTA)

作者： Agarwal, Shivangi Singh, Vijander Rani, Asha Mittal, A. P. NSIT ICE Div Sec 3 New Delhi India Univ Delhi Delhi India

The traditional signal processing algorithms suffer from large execution delay for real time issues, therefore implementation of high speed algorithms is needed. The present work aims to implement multiplier less Savitzky Golay smoothing filter (SGSF) based on distributed arithmetic (DA) for pre-processing of Electro-oculographic (EOG) signals such that speed is increased along with reduction in chip area. The filter used should be efficient enough to remove the artifacts along with least deformation from the actual signal. Savitzky-Golay (SG) filter is widely employed in biomedical signal analysis but its fast and efficient implementation is not proposed yet for EOG analysis. SGSF is selected so that disease diagnosis using saccade detection of EOG signal can be done accurately. The efficiency of proposed filter is tested in terms of signal-to-signal-plus-noise ratio (SSNR) and real time computations. It is observed from the analysis that DA based architecture increases the processing speed, reduces the chip area and original features of filtered signal are preserved.

关键词： Electro-oculography Savitzky golay filter distributed arithmetic

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The fog makes sense: Enabling social sensing services with limited internet connectivity 2

The fog makes sense: Enabling social sensing services with l...

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2nd international Workshop on Social Sensing, SocialSens 2017

作者： Mayer, Ruben Gupta, Harshit Saurez, Enrique Ramachandran, Umakishore Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Georgia Institute of Technology AtlantaGA United States

ISBN: (纸本)9781450349772

Social sensing services use humans as sensor carriers, sensor operators and sensors themselves in order to provide situation-awareness to applications. This promises to provide a multitude of benefits to the users, for example in the management of natural disasters or in community empowerment. However, current social sensing services depend on Internet connectivity since the services are deployed on central Cloud platforms. In many circumstances, Internet connectivity is constrained, for instance when a natural disaster causes Internet outages or when people do not have Internet access due to economical reasons. In this paper, we propose the emerging Fog Computing infrastructure to become a key-enabler of social sensing services in situations of constrained Internet connectivity. To this end, we develop a generic architecture and API of Fogenabled social sensing services. We exemplify the usage of the proposed social sensing architecture on a number of concrete use cases from two difierent scenarios. © 2017 ACM.

关键词： Fog computing

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Using Everest Platform for Teaching parallel and distributed Computing 22nd

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22nd international European Conference on parallel and distributed Computing (Euro-Par)

作者： Sukhoroslov, Oleg Russian Acad Sci Kharkevich Inst Inst Informat Transmiss Problems Moscow Russia Higher Sch Econ Moscow Russia

ISBN: (纸本)9783319589435;9783319589428

The paper presents a practical approach for building high-level services for teaching parallel and distributed computing based on Everest platform. Originally designed for publication of computing applications, the platform is suitable for rapid development of services for running different types of parallel programs on high-performance resources, as well as services for evaluation of practical assignments. As was demonstrated by using Everest for teaching two introductory PDC courses, the proposed approach helps to enhance students' practical experience while avoiding low-level interfaces and providing a level of automation necessary for scaling the course to a large number of students. In contrast to other solutions, the exploited Platform as a Service model provides the ability to quickly reuse this approach by other PDC educators without installation of the platform.

关键词： parallel programming distributed computing Web-based interfaces Web services Platform as a Service

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Contention-Aware Selective Caching to Mitigate Intra-Warp Contention on GPUs 16

Contention-Aware Selective Caching to Mitigate Intra-Warp Co...

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16th international symposium on parallel and distributed Computing (ISPDC)

作者： Choo, Kyoshin Troendle, David Gad, Esraa A. Jang, Byunghyun Univ Mississippi Comp & Informat Sci University MS 38677 USA

ISBN: (纸本)9781538608623

Modern GPUs embrace on-chip cache memory to exploit the locality present in applications. However, the behavior and effect of the cache on GPUs are different from those on conventional processors due to the Single Instruction Multiple Thread (SIMT) thread execution model and resulting memory access patterns. Previous studies report that caching data can hurt the performance due to increased memory traffic and thrashing on massively parallel GPUs. We found that the massive parallel thread execution of GPUs causes significant resource access contention among threads, especially within a warp. This is due to excessive demands for memory resources that are not sufficient to support massively parallel thread execution when memory access patterns are not hardware friendly. In this paper, we propose a locality and contention aware selective caching based on memory access divergence to mitigate intra-warp resource contention in L1 data (L1D) cache on GPUs. To determine when and what to cache we use the following heuristics: first, we detect memory divergence degree (i.e., how the memory requests from a warp are grouped) of the memory instruction to determine whether the selective caching is needed. Second, we use cache index calculation to handle congested cache sets. Finally, we calculate locality degree to find a better victim cache line. These algorithmic selective caching is developed based on our observation that 1) divergent memory access incurs severe contention for cache hardware resources and 2) accesses are mapped to certain sets when set associativity is relatively small compared with the memory divergence degree. Experimental results by GPU architectural simulator show that our proposed selective caching improves the average performance by 2.25x over baseline and reduces L1D cache accesses by 71%. It outperforms recently published state-of-the-art GPU cache bypassing schemes.

关键词： Instruction sets Graphics processing units Benchmark testing Kernel Resource management Indexes Ports (Computers)

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Low Area & Memory Efficient VLSI Architecture of 1D/2D DWT for Real Time Image Decomposition

Low Area & Memory Efficient VLSI Architecture of 1D/2D DWT f...

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international symposium on Electronic System Design (ISED)

作者： Anirban Chakraborty Ayan Banerjee Department of Electronics & Tele-communication Engineering Indian Institute of Engineering Science and Technology Shibpur Howrah India

ISBN: (纸本)9781538665763;9781538665756

There is a dearth of high quality reconfigurable hardware for DWT which can be extensively used in various real time signal and image processing applications. In this article, we have focused on proposing a dedicated customizable hardware for DWT applicable to 1D/2D signal processing. We have proposed bit-serial distributed Arithmetic (DA) based VLSI architectures for ID/2D DWT. Exploitation of DA enables us to make our designs Multiplierless, thereby consuming less area. Bit serial configuration of DA is also exploited to introduce modularity and pipelining in the proposed convolution DWT based 1D/2D architectures. Though the speed of the proposed designs may not be suitable for certain applications, a number of parallel channels can be introduced for the same. The provision of mode selection can efficiently be used to realize 9/7 and also 5/3 DWT filters in the same proposed architecture. In the proposed 1D/2D architecture, we have achieved about 50% memory size reduction, 30% reduction in area consumption and comparable speed in comparison to the other latest notable DWT architecture so far. We have verified the viability of our proposed 2D architecture by utilizing it in real time image decomposition.

关键词： Discrete wavelet transforms Low pass filters Read only memory Memory management Adders Two dimensional displays

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Intelligent stress calculation and scheduling in segmented processor systems using buddy approach

Intelligent stress calculation and scheduling in segmented p...

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2nd international symposium on Intelligent Systems Technologies and applications (ISTA)

作者： Bhullar, Rohit K. Pawar, Lokesh Bajaj, Rohit Manocha, Amit K. Chandigarh Univ Dept CSE Mohali Punjab India MAU Dept EEE Baddi HP India

parallel processing has been a widely studied field, used and implemented in computational systems. Many different types of topologies of processors have been implemented and their performance has been analyzed. The processor technology keeps evolving so their computational capability must be utilized accordingly when employed in parallel systems. In this article, new intra-parallel processor architectures (segmented/heterogeneous) has been used and an intelligent co-operative protocol has been implemented to optimally utilize the parallel components of the parallel processor design. More precisely a friendship based intelligent load balancing strategy has been designed and implemented to maximally utilize the parallel processor, which takes care of overloading and starvation problems and makes intelligent decisions regarding job scheduling. Context switching policies must also be designed carefully to stop performance degradation and with intelligent techniques this switching time can be reduced considerably. Work proposed in this article performs and executes load stability with feasible priori information about processors utilization, depending upon and based on this metric value the entire process space is partitioned among different categories. Based on the load status and state of affairs, processors are categorized and labeled and a suitable set out of those is figured-out that act as buddy for others and handles incoming process queue for overloaded processors. Further history and statistics of each processors is maintained and is utilized to make intelligent future scheduling decisions.

关键词： Intelligent systems parallel environment intra-processor parallelism load stability job scheduling strategy

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2nd IEEE workshop on parallel and distributed processing for computational social systems (ParSocial 2017)

Proceedings - 2017 IEEE 31st International Parallel and Dist...

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Proceedings - 2017 IEEE 31st international parallel and distributed processing symposium Workshops, IPDPSW 2017 2017年 1444-1445页

作者： Santos, Eunice E. Korah, John Illinois Institute of Technology United States

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Developing content-based recommender system using Hadoop Map Reduce

Developing content-based recommender system using Hadoop Map...

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2nd international symposium on Intelligent Systems Technologies and applications (ISTA)

作者： Gautam, Anjali Bedi, Punam Univ Delhi Dept Comp Sci Delhi India

Proliferation of information is a major confront faced by e-commerce industry. To ease the customers from this information proliferation, Recommender Systems (RS) were introduced. To improve the computational time of a RS for large scale data, the process of recommendation can be implemented on a scalable, fault tolerant and a distributed processing framework. This paper proposes a Content-Based RS implemented on scalable, fault tolerant and distributed framework of Hadoop Map Reduce. To generate recommendations with improved computational time, the proposed technique of Map Reduce Content-Based Recommendation (MRCBR) is implemented using Hadoop Map Reduce which follows the traditional process of content-based recommendation. MRCBR technique comprises of user profiling and document feature extraction which uses the vector space model followed by computing similarity to generate recommendation for the target user. Recommendations generated for the target user is a set of Top N documents. The proposed technique of recommendation is executed on a cluster of Hadoop and is tested for News dataset. News items are collected using RSS feeds and are stored in MongoDB. Computational time of MRCBR is evaluated with a Speedup factor and performance is evaluated with the standard evaluation metric of Precision, Recall and F-Measure.

关键词： Content-based RS vector space model distributed computing Hadoop Map Reduce

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