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Relaxations for High-Performance Message Passing on Massively parallel SIMT Processors

Relaxations for High-Performance Message Passing on Massivel...

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international parallel and distributed processing symposium

作者： Benjamin Klenk Holger Froning Hans Eberle Larry Dennison Inst. for Comput. Eng. Heidelberg Univ. Mannheim Germany NVIDIA Corp. Santa Clara CA USA

ISBN: (纸本)9781538639153

Accelerators, such as GPUs, have proven to be highly successful in reducing execution time and power consumption of compute-intensive applications. Even though they are already used pervasively, they are typically supervised by general-purpose CPUs, which results in frequent control flow switches and data transfers as CPUs are handling all communication tasks. However, we observe that accelerators are recently being augmented with peer-to-peer communication capabilities that allow for autonomous traffic sourcing and sinking. While appropriate hardware support is becoming available, it seems that the right communication semantics are yet to be identified. Maintaining the semantics of existing communication models, such as the Message Passing Interface (MPI), seems problematic as they have been designed for the CPU's execution model, which inherently differs from such specialized processors. In this paper, we analyze the compatibility of traditional message passing with massively parallel Single Instruction Multiple Thread (SIMT) architectures, as represented by GPUs, and focus on the message matching problem. We begin with a fully MPI-compliant set of guarantees, including tag and source wildcards and message ordering. Based on an analysis of exascale proxy applications, we start relaxing these guarantees to adapt message passing to the GPU's execution model. We present suitable algorithms for message matching on GPUs that can yield matching rates of 60M and 500M matches/s, depending on the constraints that are being relaxed. We discuss our experiments and create an understanding of the mismatch of current message passing protocols and the architecture and execution model of SIMT processors.

关键词： Heterogeneous systems GPU Computing Communication Models Message Passing

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Transparent heterogeneous backing store for file systems

Transparent heterogeneous backing store for file systems

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Benjamin Marks Tia Newhall Computer Science Department Swarthmore College Swarthmore PA USA

We present Nswap2L-FS, a fast, adaptable, and heterogeneous storage system for backing file data in clusters. Nswap2L-FS particularly targets backing temporary files, such as those created by data-intensive applications for storing intermediate results. Our work addresses the problem of how to efficiently and effectively make use of heterogeneous storage devices that are increasingly common in clusters. Nswap2L-FS implements a two-layer device design. The top layer transpar- ently manages a set of bottom layer physical storage devices, which may include SSD, HDD, and its own implementation of network RAM. Nswap2L-FS appears to node operating systems as a single, fast backing storage device for file systems, hiding the complexity of heterogeneous storage management from OS subsystems. Internally, it implements adaptable and tunable policies that specify where data should be placed and whether data should be migrated from one underlying physical device to another based on resource usage and the characteristics of different devices. We present solutions to challenges that are specific to supporting backing filesystems, including how to efficiently support a wide range of I/O request sizes and balancing fast storage goals with expectations of persistence of stored file data. Nswap2L-FS defines relaxed persistence guarantees on individual file writes to achieve faster I/O accesses; less stringent persistence semantics allow it to make use of network RAM to store file data, resulting in faster file I/O to applications. Relaxed persistence guarantees are acceptable in many situations, particularly those involving short-lived data such as temporary files. Nswap2L-FS provides a persistence snapshot mechanism that can be used by applications or checkpointing systems to ensure that file data are persistent at certain points in their execution. Nswap2L-FS is implemented as a Linux block device driver that can be added as a file partition on individual cluster nodes. Experimenta

关键词： Random access memory Performance evaluation distributed databases Operating systems Complexity theory Checkpointing Context

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Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study

Exploiting Decoupled OpenCL Work-Items with Data Dependencie...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Javier Alejandro Varela Norbert Wehn Qian Liang Songyin Tang Microelectronic Systems Design Research Group University of Kaiserslautern Germany BearingPoint GmbH Germany

In the field of high performance heterogeneous computing systems, field programmable gate arrays (FPGAs) have shown great advantages in terms of acceleration and energy efficiency. And with the inclusion of the OpenCL framework for parallel programming, the design complexity has been greatly reduced. However, the parallel implementation of applications containing data-dependent branches usually experiences an important loss in performance, which affects all platforms alike. This data dependency leads the execution of parallel threads, also called work-items in OpenCL, to diverge. Whereas fixed architectures like CPU, GPU and Xeon Phi cannot efficiently cope with this divergent execution, the flexibility offered by FPGAs in terms of architecture can be exploited to tackle this problem. In this work, we present a new approach for FPGA implementations that decouples the parallel OpenCL work-items, avoiding the interference of data-dependent branches between them. We also demonstrate the necessary workarounds to obtain the maximum performance in a pipelined design, when unpredictable for-loop exit conditions are caused by the data dependency. Furthermore, we show how to efficiently interleave computation with transfers to device global memory in each work-item. This approach is then evaluated with a real-life case study from Finance, with four different configurations implemented on FPGA with Xilinx SDAccel, and compared to the optimized implementation on CPU, GPU, and Xeon Phi. Our results show that FPGAs can deliver up to 5.5x speedup, whereas the system-level energy efficiency increases between 2x and 9.5x in all cases.

关键词： Field programmable gate arrays Computer architecture Hardware Graphics processing units Kernel parallel programming Runtime

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High Performance Molecular Visualization: In-Situ and parallel Rendering with EGL 30

High Performance Molecular Visualization: In-Situ and Parall...

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30th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Stone, John E. Messmer, Peter Sisneros, Robert Schulten, Klaus Univ Illinois Beckman Inst Urbana IL 61801 USA NVIDIA Dev Technol Grp Zurich Switzerland Univ Illinois Natl Ctr Supercomp Applicat Urbana IL USA Univ Illinois Dept Phys Urbana IL USA

ISBN: (纸本)9781509036820

Large scale molecular dynamics simulations produce terabytes of data that is impractical to transfer to remote facilities. It is therefore necessary to perform visualization tasks in-situ as the data are generated, or by running interactive remote visualization sessions and batch analyses co-located with direct access to high performance storage systems. A significant challenge for deploying visualization software within clouds, clusters, and supercomputers involves the operating system software required to initialize and manage graphics acceleration hardware. Recently, it has become possible for applications to use the Embedded-system Graphics Library (EGL) to eliminate the requirement for windowing system software on compute nodes, thereby eliminating a significant obstacle to broader use of high performance visualization applications. We outline the potential benefits of this approach in the context of visualization applications used in the cloud, on commodity clusters, and supercomputers. We discuss the implementation of EGL support in VMD, a widely used molecular visualization application, and we outline benefits of the approach for molecular visualization tasks on petascale computers, clouds, and remote visualization servers. We then provide a brief evaluation of the use of EGL in VMD, with tests using developmental graphics drivers on conventional workstations and on Amazon EC2 G2 GPU-accelerated cloud instance types. We expect that the techniques described here will be of broad benefit to many other visualization applications.

关键词： in-situ visualization remote visualization parallel rendering molecular visualization

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GraphPad: Optimized Graph Primitives for parallel and distributed Platforms 30

GraphPad: Optimized Graph Primitives for Parallel and Distri...

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30th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Anderson, Michael J. Sundaram, Narayanan Satish, Nadathur Patwary, Md Mostofa Ali Willke, Theodore L. Dubey, Pradeep Intel Corp Parallel Comp Lab Santa Clara CA 95052 USA

ISBN: (纸本)9781509021406

The duality between graphs and matrices means that many common graph analyses can be expressed with primitives such as generalized sparse matrix-vector multiplication (SpMSpV) and sparse matrix-matrix multiplication (SpGEMM). Achieving high performance on these primitives is challenging due to limited arithmetic intensity, irregular memory accesses, and significant network communication requirements in the distributed setting. In this paper we implement four graph applications using GraphPad, our optimized multinode implementations of generalized linear algebra primitives such as SpMSpV and SpGEMM. GraphPad is highly flexible to accommodate multiple data layouts, partitioning strategies, and incorporates communication optimizations. Our performance at scale can exceed that of CombBLAS by up to 40x. In addition to GraphPad's performance in a distributed setting, it is also within 2x the performance of GraphMat, a high performance graph framework on a single node for four out of five benchmarks. We also show our communication optimizations and flexibility are critical for good performance on both HPC clusters and commodity cloud platforms.

关键词： Graph analytics SpGEMM SpMSpV

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Power Efficient Sharing-Aware GPU Data Management

Power Efficient Sharing-Aware GPU Data Management

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international symposium on parallel and distributed processing (IPDPS)

作者： Abdulaziz Tabbakh Murali Annavaram Xuehai Qian Electrical Engineering Department University of Southern California Los Angeles USA

The power consumed by memory system in GPUs is a significant fraction of the total chip power. As thread level parallelism increases, GPUs are likely to stress cache and memory bandwidth even more, thereby exacerbating power consumption. We observe that neighboring concurrent thread arrays (CTAs) within GPU applications share considerable amount of data. However, the default GPU scheduling policy spreads these CTAs to different streaming multiprocessor cores (SM) in a round-robin fashion. Since each SM has a private L1 cache, the shared data among CTAs are replicated across L1 caches of different SMs. Data replication reduces the effective L1 cache size which in turn increases the data movement and power consumption. The goal of this paper is to reduce data movement and increase effective cache space in GPUs. We propose a sharing-aware CTA scheduler that attempts to assign CTAs with data sharing to the same SM to reduce redundant storage of data in private L1 caches across SMs. We further enhance the scheduler with a sharing-aware cache allocation and replacement policy. The sharing-aware cache management approach dynamically classifies private and shared data. Private blocks are given higher priority to stay longer in L1 cache, and shared blocks are given higher priority to stay longer in L2 cache. Essentially, this approach increases the lifetime of shared blocks and private blocks in different cache levels. The experimental results show that the proposed scheme reduces the off-chip traffic by 19\% which translates to an average DRAM power reduction of 10% and performance improvement of 7%.

关键词： Graphics processing units Kernel Instruction sets Resource management Benchmark testing Random access memory Arrays

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A GPU based maximum common subgraph algorithm for drug discovery applications 30

A GPU based maximum common subgraph algorithm for drug disco...

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30th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Jayaraj, P. B. Rahamathulla, K. Gopakumar, G. Natl Inst Technol Calicut Dept Comp Sci & Engn Calicut Kerala India

ISBN: (纸本)9781509036820

The maximum common subgraph of two graphs, G(1) and G(2), is the largest subgraph in G(1) that is isomorphic to a subgraph in G(2). Finding the maximum common subgraph of two given graphs is known to be a NP-complete problem. An exact solution for the maximum common subgraph problem can be found by an algorithm that transforms the maximum common subgraph problem into a maximal clique enumeration problem. However, as the size of the graph increases, the solution space of the maximal clique enumeration problem increases combinatorially. A serial solution to the computationally intensive problem of complete maximal clique enumeration is tedious. This paper presents a parallel approach using Graphic processing Unit to compute the maximum common subgraph of the given graphs. The parallel procedure achieves more than tenfold improvement in computational performance. As an application of the proposed parallel maximum common subgraph algorithm, two new tools;LIGAndMATCHER and GRAPHSCREEN are developed. These tools can be used to narrow down the large ligand search space to a small number in the screening phase of drug discovery process.

关键词： Maximum Common Subgraph Maximal Clique Enumeration GPU CUDA Ligand Matching Virtual Screening

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Application Fault Tolerance for Shrinking Resources via the Sparse Grid Combination Technique 30

Application Fault Tolerance for Shrinking Resources via the ...

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30th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Strazdins, Peter E. Ali, Md Mohsin Debusschere, Bert Australian Natl Univ Res Sch Comp Sci Canberra ACT 0200 Australia Sandia Natl Labs Combust Res Facil Livermore CA USA

ISBN: (纸本)9781509036820

The need to make large-scale scientific simulations resilient to the shrinking and growing of compute resources arises from exascale computing and adverse operating conditions (fault tolerance). It can also arise from the cloud computing context where the cost of these resources can fluctuate. In this paper, we describe how the Sparse Grid Combination Technique can make such applications resilient to shrinking compute resources. The solution of the non-trivial issues of dealing with data redistribution and on-the-fly malleability of process grid information and ULFM MPI communicators are described. Results on a 2D advection solver indicate that process recovery time is significantly reduced from the alternate strategy where failed resources are replaced, overall execution time is actually improved from this case and for checkpointing and the execution error remains small, even when multiple failures occur.

关键词： algorithm-based fault tolerance ULFM process failure recovery PDE solvers sparse grid combination technique parallel computing elasticity cloud computing

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More Effective Synchronization Scheme in ML using Stale Parameters

More Effective Synchronization Scheme in ML using Stale Para...

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18th IEEE international Conference on High Performance Computing and Communications (HPCC) / 14th IEEE international Conference on Smart City (Smart City) / 2nd IEEE international Conference on Data Science and Systems (DSS)

作者： Li, Yabin Wan, Han Jiang, Bo Long, Xiang Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781509042975

In Machine learning (ML) the model we use is increasingly important, and the model's parameters, the key point of the ML, are adjusted through iteratively processing a training dataset until convergence. Although data-parallel ML systems often engage a perfect error tolerance when synchronizing the model parameters for maximizing parallelism, the synchronization of model parameters may delay in completion, a problem that generally gets worse at a large scale. This paper presents a Bounded Asynchronous parallel (BAP) model of computation that allows computations using stale model parameters in order to reduce synchronization overheads. In the meanwhile, our BAP model ensures theoretical convergence guarantees for large scale data-parallel ML applications. This model permits distributed workers to use the stale parameters storing in the local cache, instead of waiting until the Parameter Server (PS) produces a new version. This expressively reduces the time workers spend on waiting. Furthermore, the BAP model guarantees the convergence of ML algorithm by bounding the maximum distance of the stale parameters. Experiments conducted on 4 cluster nodes with up to 32 GPUs showed that our model significantly improved the proportion of computing time relative to the waiting time and led to 1.2-2 X speedup. Besides, we elaborated how to choose the staleness threshold when considering the tradeoff between Efficiency and Speed.

关键词： distributed systems Bounded Asynchronous parallel Bulk Synchronous parallel Total Asynchronous parallel stale parameters tradeoff

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Communication-Avoiding parallel Sparse-Dense Matrix-Matrix Multiplication 30

Communication-Avoiding Parallel Sparse-Dense Matrix-Matrix M...

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30th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Koanantakool, Penporn Azad, Ariful Buluc, Aydin Morozov, Dmitriy Oh, Sang-Yun Oliker, Leonid Yelick, Katherine Lawrence Berkeley Natl Lab Computat Res Div Berkeley CA 94720 USA Univ Calif Berkeley Dept EECS Berkeley CA 94720 USA Univ Calif Santa Barbara Dept Stat & Appl Probabil Santa Barbara CA 93106 USA

ISBN: (纸本)9781509021406

Multiplication of a sparse matrix with a dense matrix is a building block of an increasing number of applications in many areas such as machine learning and graph algorithms. However, most previous work on parallel matrix multiplication considered only both dense or both sparse matrix operands. This paper analyzes the communication lower bounds and compares the communication costs of various classic parallel algorithms in the context of sparse-dense matrix-matrix multiplication. We also present new communication-avoiding algorithms based on a 1D decomposition, called 1.5D, which - while suboptimal in dense-dense and sparse-sparse cases - outperform the 2D and 3D variants both theoretically and in practice for sparsedense multiplication. Our analysis separates one-time costs from per iteration costs in an iterative machine learning context. Experiments demonstrate speedups up to 100x over a baseline 3D SUMMA implementation and show parallel scaling over 10 thousand cores.

关键词： Communication-avoiding algorithms Linear algebra parallel algorithms Sparse-dense matrix-matrix multiplication

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