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More Effective Synchronization Scheme in ML using Stale Parameters

More Effective Synchronization Scheme in ML using Stale Para...

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IEEE international Conference on High Performance Computing and Communications

作者： Yabin Li Han Wan Bo Jiang Xiang Long Sch. of Comput. Sci. & Eng. Beihang Univ. Beijing China

ISBN: (纸本)9781509042982

In Machine learning (ML) the model we use is increasingly important, and the model's parameters, the key point of the ML, are adjusted through iteratively processing a training dataset until convergence. Although data-parallel ML systems often engage a perfect error tolerance when synchronizing the model parameters for maximizing parallelism, the synchronization of model parameters may delay in completion, a problem that generally gets worse at a large scale. This paper presents a Bounded Asynchronous parallel (BAP) model of computation that allows computations using stale model parameters in order to reduce synchronization overheads. In the meanwhile, our BAP model ensures theoretical convergence guarantees for large scale data-parallel ML applications. This model permits distributed workers to use the stale parameters storing in the local cache, instead of waiting until the Parameter Server (PS) produces a new version. This expressively reduces the time workers spend on waiting. Furthermore, the BAP model guarantees the convergence of ML algorithm by bounding the maximum distance of the stale parameters. Experiments conducted on 4 cluster nodes with up to 32 GPUs showed that our model significantly improved the proportion of computing time relative to the waiting time and led to 1.2-2 X speedup. Besides, we elaborated how to choose the staleness threshold when considering the tradeoff between Efficiency and Speed.

关键词： tradeoff distributed systems Bounded Asynchronous parallel Bulk Synchronous parallel Total Asynchronous parallel stale parameters

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A GPU Based Maximum Common Subgraph Algorithm for Drug Discovery applications

A GPU Based Maximum Common Subgraph Algorithm for Drug Disco...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： P. B. Jayaraj K. Rahamathulla G. Gopakumar Department of Computer Science and Engineering National Institute of Technology Calicut India

ISBN: (纸本)9781509036837

The maximum common subgraph of two graphs, G 1 and G 2 , is the largest subgraph in G 1 that is isomorphic to a subgraph in G 2 . Finding the maximum common subgraph of two given graphs is known to be a NP-complete problem. An exact solution for the maximum common subgraph problem can be found by an algorithm that transforms the maximum common subgraph problem into a maximal clique enumeration problem. However, as the size of the graph increases, the solution space of the maximal clique enumeration problem increases combinatorially. A serial solution to the computationally intensive problem of complete maximal clique enumeration is tedious. This paper presents a parallel approach using Graphic processing Unit to compute the maximum common subgraph of the given graphs. The parallel procedure achieves more than tenfold improvement in computational performance. As an application of the proposed parallel maximum common subgraph algorithm, two new tools, LIGAndMATCHER and GRAPHSCREEN are developed. These tools can be used to narrow down the large ligand search space to a small number in the screening phase of drug discovery process.

关键词： Graphics processing units Instruction sets Search problems Kernel parallel algorithms Algorithm design and analysis Drugs

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HPGraph: A High parallel Graph processing System Based on Flash Array

HPGraph: A High Parallel Graph Processing System Based on Fl...

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IEEE international Conference on High Performance Computing and Communications (HPCC)

作者： Yuxuan Xing Ya Feng Songping Yu Zhengguo Chen Fang Liu Nong Xiao State Key Laboratory of High Performance Computing National University of Defense Technology NUDT Changsha China National University of Defense Technology Changsha Hunan CN

ISBN: (纸本)9781509042982

Large graphs analytics has been an important aspect of many big data applications, such as web search, social networks and recommendation systems. Many research focuses on processing large scale graphs using distributed system over past few years. And numbers of studies turn to construct graph processing system on a single server-class machine in consideration of cost, usability and maintainability. HPGraph is a high parallel graph processing system which adopts the edge-centric model, our contributions are as follows: (1) designing an efficient data allocation and access strategy for NUMA machine, and providing tasks scheduling to keep load balance, (2) raising a fine-grained edge-block filtering mechanism to avoid accessing unnecessary edge data, (3) constructing a high-speed flash array as the second storage. We made a detailed evaluation on a 16-core machine using asset of popular real word and synthetic data sets, and the results show that HPGraph always outperforms the state-of-the-art single machine graph processing systems-GridGraph. And HPGraph can achieve 1.27X faster than GridGraph for specific application. Our source code is available at https://***/xinghuan1990/HPGraph.

关键词： Conferences High performance computing Smart cities Data science

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High Performance Molecular Visualization: In-Situ and parallel Rendering with EGL

High Performance Molecular Visualization: In-Situ and Parall...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： John E. Stone Peter Messmer Robert Sisneros Klaus Schulten Beckman Institute University of Illinois at Urbana-Champaign Urbana IL Developer Technology Group NVIDIA Zurich Switzerland National Center for Supercomputing Applications University of Illinois at Urbana-Champaign Urbana IL Department of Physics University of Illinois at Urbana-Champaign Urbana IL

ISBN: (纸本)9781509036837

Large scale molecular dynamics simulations produce terabytes of data that is impractical to transfer to remote facilities. It is therefore necessary to perform visualization tasks in-situ as the data are generated, or by running interactive remote visualization sessions and batch analyses co-located with direct access to high performance storage systems. A significant challenge for deploying visualization software within clouds, clusters, and supercomputers involves the operating system software required to initialize and manage graphics acceleration hardware. Recently, it has become possible for applications to use the Embedded-system Graphics Library (EGL) to eliminate the requirement for windowing system software on compute nodes, thereby eliminating a significant obstacle to broader use of high performance visualization applications. We outline the potential benefits of this approach in the context of visualization applications used in the cloud, on commodity clusters, and supercomputers. We discuss the implementation of EGL support in VMD, a widely used molecular visualization application, and we outline benefits of the approach for molecular visualization tasks on petascale computers, clouds, and remote visualization servers. We then provide a brief evaluation of the use of EGL in VMD, with tests using developmental graphics drivers on conventional workstations and on Amazon EC2 G2 GPU-accelerated cloud instance types. We expect that the techniques described here will be of broad benefit to many other visualization applications.

关键词： Data visualization Software Servers Rendering (computer graphics) Supercomputers Libraries

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Hessenberg Reduction with Transient Error Resilience on GPU-Based Hybrid Architectures

Hessenberg Reduction with Transient Error Resilience on GPU-...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Yulu Jia Piotr Luszczek Jack Dongarra University of Tennessee USA University of Manchester UK Oak Ridge National Laboratory USA

ISBN: (纸本)9781509036837

Graphics processing Units (GPUs) have been seeing widespread adoption in the field of scientific computing, owing to the performance gains provided on computation-intensive applications. In this paper, we present the design and implementation of a Hessenberg reduction algorithm immune to simultaneous soft-errors, capable of taking advantage of hybrid GPU-CPU platforms. These soft-errors are detected and corrected on the fly, preventing the propagation of the error to the rest of the data. Our design is at the intersection between several fault tolerant techniques and employs the algorithm-based fault tolerance technique, diskless checkpointing, and reverse computation to achieve its goal. By utilizing the idle time of the CPUs, and by overlapping both host-side and GPU-side workloads, we minimize the resilience overhead. Experimental results have validated our design decisions as our algorithm introduced less than 2% performance overhead compared to the optimized, but fault-prone, hybrid Hessenberg reduction.

关键词： Algorithm design and analysis Fault tolerance Fault tolerant systems Transient analysis Transistors Central processing Unit Graphics processing units

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Hybrid Dynamic Trees for Extreme-Resolution 3D Sparse Data Modeling

Hybrid Dynamic Trees for Extreme-Resolution 3D Sparse Data M...

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international symposium on parallel and distributed processing (IPDPS)

作者： Mohammad M. Hossain Thomas M. Tucker Thomas R. Kurfess Richard W. Vuduc School of Computer Science Georgia Institute of Technology Atlanta GA USA Tucker Innovations Inc. Charlotte NC USA School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA School of Computational Science and Engineering Georgia Institute of Technology Atlanta GA USA

ISBN: (纸本)9781509021413

This paper presents the hybrid dynamic tree (HDT), a novel adaptive tree-based data structure for representing high-resolution sparse volumes. Roughly speaking, HDTs combine dense volumetric grids with sparse octrees in a way that makes them both more compact and better-suited to GPUs than state-of-the-art alternatives. For our motivating applications in computer-aided design and manufacturing(CAD/CAM), we show 2× reductions in storage on realistic inputs compared to these alternatives, additionally, we show up to 16 fix speedups over multicore CPU implementations on a specific computational bottleneck known as an offset surface computation. Indeed, these combined improvements allow us to perform offsetting on a single node at resolutions well beyond that of the prior work and the capabilities of current commercial packages. And beyond CAD/CAM, HDTs may find applications in 3D geometric modeling problems for a variety of domains, including medical imaging and graphics.

关键词： Octrees Microprocessors Graphics processing units Vegetation Topology Three-dimensional displays

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Communication-Avoiding parallel Sparse-Dense Matrix-Matrix Multiplication

Communication-Avoiding Parallel Sparse-Dense Matrix-Matrix M...

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international symposium on parallel and distributed processing (IPDPS)

作者： Penporn Koanantakool Ariful Azad Aydin Buluç Dmitriy Morozov Sang-Yun Oh Leonid Oliker Katherine Yelick Computational Research Division Lawrence Berkeley National Laboratory Berkeley USA EECS Department University of California Berkeley USA Department of Statistics and Applied Probability University of California Santa Barbara USA

ISBN: (纸本)9781509021413

Multiplication of a sparse matrix with a dense matrix is a building block of an increasing number of applications in many areas such as machine learning and graph algorithms. However, most previous work on parallel matrix multiplication considered only both dense or both sparse matrix operands. This paper analyzes the communication lower bounds and compares the communication costs of various classic parallel algorithms in the context of sparse-dense matrix-matrix multiplication. We also present new communication-avoiding algorithms based on a 1D decomposition, called 1.5D, which - while suboptimal in dense-dense and sparse-sparse cases - outperform the 2D and 3D variants both theoretically and in practice for sparse-dense multiplication. Our analysis separates one-time costs from per iteration costs in an iterative machine learning context. Experiments demonstrate speedups up to 100x over a baseline 3D SUMMA implementation and show parallel scaling over 10 thousand cores.

关键词： Sparse matrices Three-dimensional displays Partitioning algorithms Algorithm design and analysis Machine learning algorithms parallel algorithms Covariance matrices

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TintMalloc: Reducing Memory Access Divergence via Controller-Aware Coloring

TintMalloc: Reducing Memory Access Divergence via Controller...

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international symposium on parallel and distributed processing (IPDPS)

作者： Xing Pan Yasaswini Jyothi Gownivaripalli Frank Mueller Dept. of Computer Science North Carolina State University Raleigh NC USA

ISBN: (纸本)9781509021413

DRAM memory of modern multicores is partitioned into sets, each with its own memory controller governing multiple banks. Accesses can be served in parallel to controllers and banks, but sharing of either between threads results in contention that increases latency, and so do accesses to remote controllers due to the non-uniform memory access (NUMA) design. Above DRAM, a last-level cache (LLC), typically at level 3 (L3), is shared by all cores while L1 and L2 caches tend to be core private. This NUMA design inflicts significant variations in execution time for applications with large datasets due to different latencies incurred by remote memory node accesses or contention in LLC and at memory banks/controllers. As a result, single program multiple data (SPMD) applications tend to experience computational imbalance at barriers, which inflicts idle (wait) time for threads that at barriers arrive early and thus impairs effective processor utilization and ultimately performance. This work contributes a novel memory allocator called Tint-Malloc that colors memory at the LLC, bank, and controller level to ensure locality to the local memory node while reducing contention at the LLC/bank levels in software. After adding one line of code during initialization in each thread, existing applications automatically obtain colored heap space through regular malloc calls. Experimental results with the SPEC and Parsec benchmarks show that by choosing disjoint colors per thread, locality is increased, contention is decreased, and overall SPMD execution becomes more balanced atbarriers than default memory allocation under Linux as well as prior coloring approaches.

关键词： Instruction sets Image color analysis Random access memory Multicore processing Sockets Resource management Registers

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Towards a distributed Large-Scale Dynamic Graph Data Store

Towards a Distributed Large-Scale Dynamic Graph Data Store

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Keita Iwabuchi Scott Sallinen Roger Pearce Brian Van Essen Maya Gokhale Satoshi Matsuoka Tokyo Institute of Technology Center for Applied Scientific Computing Lawrence Livermore National Laboratory University of British Columbia Center for Appl. Sci. Comput. Lawrence Livermore National Laboratory Livermore CA US Global Scientific Information and Computing Center Tokyo Institute of Technology

ISBN: (纸本)9781509036837

In many graph applications, the structure of the graph changes dynamically over time and may require real time analysis. However, constructing a large graph is expensive, and most studies for large graphs have not focused on a dynamic graph data structure, but rather a static one. To address this issue, we propose DegAwareRHH, a high performance dynamic graph data store designed for scaling out to store large, scale-free graphs by leveraging compact hash tables with high data locality. We extend DegAwareRHH for multiple processes and distributed memory, and perform dynamic graph construction on large scale-free graphs using emerging 'Big Data HPC' systems such as the Catalyst cluster at LLNL. We demonstrate that DegAwareRHH processes a request stream 206.5x faster than a state-of-the-art shared-memory dynamic graph processing framework, when both implementations use 24 threads/processes to construct a graph with 1 billion edge insertion requests and 54 million edge deletion requests. DegAwareRHH also achieves a processing rate of over 2 billion edge insertion requests per second using 128 compute nodes to construct a large-scale web graph, containing 128 billion edges, the largest open-source real graph dataset to our knowledge.

关键词： Probes Random access memory Arrays Nonvolatile memory Indexes Data models

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Compiler-Assisted Workload Consolidation for Efficient Dynamic parallelism on GPU

Compiler-Assisted Workload Consolidation for Efficient Dynam...

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international symposium on parallel and distributed processing (IPDPS)

作者： Hancheng Wu Da Li Michela Becchi Dept. of Electrical and Computer Engineering University of Missouri Columbia MO USA

ISBN: (纸本)9781509021413

GPUs have been widely used to accelerate computations exhibiting simple patterns of parallelism -- such as flat or two-level parallelism -- and a degree of parallelism that can be statically determined based on the size of the input dataset. However, the effective use of GPUs for algorithms exhibiting complex patterns of parallelism, possibly known only at runtime, is still an open problem. Recently, Nvidia has introduced Dynamic parallelism (DP) in its GPUs. By making it possible to launch kernels directly from GPU threads, this feature enables nested parallelism at runtime. However, the effective use of DP must still be understood: a naïve use of this feature may suffer from significant runtime overhead and lead to GPU underutilization, resulting in poor performance. In this work, we target this problem. First, we demonstrate how a naïve use of DP can result in poor performance. Second, we propose three workload consolidation schemes to improve performance and hardware utilization of DP-based codes, and we implement these code transformations in a directive-based compiler. Finally, we evaluate our framework on two categories of applications: algorithms including irregular loops and algorithms exhibiting parallel recursion. Our experiments show that our approach significantly reduces runtime overhead and improves GPU utilization, leading to speedup factors from 90x to 3300x over basic DP-based solutions and speedups from 2x to 6x over flat implementations.

关键词： Kernel Graphics processing units parallel processing Instruction sets Runtime Hardware Synchronization

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