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FuzzyGPU: a fuzzy arithmetic library for GPU

FuzzyGPU: a fuzzy arithmetic library for GPU

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22nd Euromicro international Conference on parallel, distributed, and Network-Based processing (PDP)

作者： Defour, David Marin, Manuel Univ Perpignan DALI F-66860 Perpignan France Univ Montpellier 2 LIRMM UMR 5506 F-34095 Montpellier France CNRS LIRMM UMR 5506 F-34095 Montpellier France

ISBN: (纸本)9781479927289

Data are traditionally represented using native format such as integer or floating-point numbers in various flavor. However, some applications rely on more complex representation format. This is the case when uncertainty needs to be apprehended. Fuzzy arithmetic is one of the major tools to address this problem, but the execution time of basic operations such as addition or multiplication makes its usage prohibitive. In this article, thanks to a new representation format and modern GPU characteristics we show that it is possible to greatly reduce the execution time of those operations. These techniques have been implemented in fuzzyGPU, a freely distributed library of common operations over fuzzy number.

关键词： floating point arithmetic fuzzy set theory graphics processing units number theory addition operation execution time reduction floating-point numbers fuzzy arithmetic library fuzzy number fuzzyGPU integer numbers multiplication operation representation format uncertainty management usage prohibitive Encoding Graphics processing units Kernel Libraries Memory management Uncertainty

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CyGraph: A Reconfigurable Architecture for parallel Breadth-First Search 28

CyGraph: A Reconfigurable Architecture for Parallel Breadth-...

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28th IEEE international parallel & distributed processing symposium Workshops (IPDPSW)

作者： Attia, Osama G. Johnson, Tyler Townsend, Kevin Jones, Philip Zambreno, Joseph Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

ISBN: (纸本)9781479941162

Large-scale graph structures are considered as a keystone for many emerging high-performance computing applications in which Breadth-First Search (BFS) is an important building block. For such graph structures, BFS operations tends to be memory-bound rather than compute-bound. In this paper, we present an efficient reconfigurable architecture for parallel BFS that adopts new optimizations for utilizing memory bandwidth. Our architecture adopts a custom graph representation based on compressed-sparse raw format (CSR), as well as a restructuring of the conventional BFS algorithm. By taking maximum advantage of available memory bandwidth, our architecture continuously keeps our processing elements active. Using a commercial high-performance reconfigurable computing system (the Convey HC-2), our results demonstrate a 5x speedup over previously published FPGA-based implementations.

关键词： Reconfigurable Computing Breadth-First Search Graphs FPGA Convey HC-2

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FMI: Fault Tolerant Messaging Interface for Fast and Transparent Recovery

FMI: Fault Tolerant Messaging Interface for Fast and Transpa...

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IEEE 28th international parallel & distributed processing symposium (IPDPS)

作者： Sato, Kento Moody, Adam Mohror, Kathryn Gamblin, Todd de Supinski, Bronis R. Maruyama, Naoya Matsuoka, Satoshi Tokyo Inst Technol Dep Math & Comp Sci Meguro Ku 2-12-1-W8-33 Ohokayama Tokyo 1528552 Japan Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA RIKEN Adv Inst Computat Sci Kobe Hyogo 6500047 Japan Tokyo Inst Technol Global Sci Informat & Comp Ctr Meguro Ku Tokyo 1528552 Japan

ISBN: (纸本)9780769552071

Future supercomputers built with more components will enable larger, higher-fidelity simulations, but at the cost of higher failure rates. Traditional approaches to mitigating failures, such as checkpoint/restart (C/R) to a parallel file system incur large overheads. On future, extreme-scale systems, it is unlikely that traditional C/R will recover a failed application before the next failure occurs. To address this problem, we present the Fault Tolerant Messaging Interface (FMI), which enables extremely low-latency recovery. FMI accomplishes this using a survivable communication runtime coupled with fast, in-memory C/R, and dynamic node allocation. FMI provides message-passing semantics similar to MPI, but applications written using FMI can run through failures. The FMI runtime software handles fault tolerance, including checkpointing application state, restarting failed processes, and allocating additional nodes when needed. Our tests show that FMI runs with similar failure-free performance as MPI, but FMI incurs only a 28% overhead with a very high mean time between failures of 1 minute.

关键词： Fault tolerance MPI Checkpoint/Restart

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Generalizing Run-time Tiling with the Loop Chain Abstraction

Generalizing Run-time Tiling with the Loop Chain Abstraction

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IEEE 28th international parallel & distributed processing symposium (IPDPS)

作者： Strout, Michelle Mills Luporini, Fabio Krieger, Christopher D. Bertolli, Carlo Bercea, Gheorghe-Teodor Olschanowsky, Catherine Ramanujam, J. Kelly, Paul H. J. Colorado State Univ Ft Collins CO 80523 USA Univ London Imperial Coll Sci Technol & Med London SW7 2AZ England IBM T J Watson Res Los Angeles CA USA Louisiana State Univ Baton Rouge LA 70803 USA

ISBN: (纸本)9780769552071

Many scientific applications are organized in a data parallel way: as sequences of parallel and/or reduction loops. This exposes parallelism well, but does not convert data reuse between loops into data locality. This paper focuses on this issue in parallel loops whose loop-to-loop dependence structure is data-dependent due to indirect references such as A[B[i]]. Such references are a common occurrence in sparse matrix computations, molecular dynamics simulations, and unstructured-mesh computational fluid dynamics (CFD). Previously, sparse tiling approaches were developed for individual benchmarks to group iterations across such loops to improve data locality. These approaches were shown to benefit applications such as moldyn, Gauss-Seidel, and the sparse matrix powers kernel, however the run-time routines for performing sparse tiling were hand coded per application. In this paper, we present a generalized full sparse tiling algorithm that uses the newly developed loop chain abstraction as input, improves inter-loop data locality, and creates a task graph to expose shared-memory parallelism at runtime. We evaluate the overhead and performance impact of the generalized full sparse tiling algorithm on two codes: a sparse Jacobi iterative solver and the Airfoil CFD benchmark.

关键词： inspector/executor run-time reordering transformations tiling

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Analytic Clock Frequency Selection for Global DVFS

Analytic Clock Frequency Selection for Global DVFS

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22nd Euromicro international Conference on parallel, distributed, and Network-Based processing (PDP)

作者： Gerards, Marco E. T. Hurink, Johann L. Holzenspies, Philip K. F. Kuper, Jan Smit, Gerard J. M. Univ Twente Dept EEMCS NL-7500 AE Enschede Netherlands

ISBN: (纸本)9781479927289

Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors. There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.

关键词： Dynamic voltage and frequency scaling energy minimization mathematical programming parallel processing

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Fast Epistasis Detection in Large-Scale GWAS for Intel Xeon Phi Clusters

Fast Epistasis Detection in Large-Scale GWAS for Intel Xeon ...

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IEEE international symposium on parallel and distributed processing with applications

作者： Glenn R. Luecke Nathan T. Weeks Brandon M. Groth Marina Kraeva Li Ma Luke M. Kramer James E. Koltes James M. Reecy Department of Mathematics Iowa State University USA IT Services Academic Technologies Iowa State University USA Department of Animal Science Iowa State University USA Department of Animal and Avian Sciences University of Maryland USA

ISBN: (纸本)9781467379533

epiSNP is a program for identifying pairwise single nucleotide polymorphism (SNP) interactions (epistasis) that affect quantitative traits in genome-wide association studies (GWAS). A parallel MPI version (EPISNPmpi) was created in 2008 to address this computationally-expensive analysis on data sets with many quantitative traits and markers. However, the explosion in genome sequencing will lead to the creation of large-scale data sets that will overwhelm EPISNPmpi's ability to compute results in a reasonable amount of time. Thus, epiSNP was rewritten to efficiently handle these large data sets. This was accomplished by performing serial optimizations, improving MPI load balancing, and introducing parallel OpenMP directives to further enhance load balancing and allow execution on the Intel Xeon Phi coprocessor (MIC). These additions resulted in new scalable versions of epiSNP using MPI, MPI+OpenMP, and MPI+OpenMP with one or two MICs. For a large 774,660 SNP data set with 1,634 individuals, the runtime on 126 nodes of TACC's Stampede Supercomputer was 10.61 minutes without MICs, and 5.13 minutes with 2 MICs. This translated to speedups over EPISNPmpi of 17X without MICs, and 36X with 2 MICs.

关键词： Xeon Phi coprocessor epistasis GWAS MPI OpenMP parallel Computing

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Comparison of parallel Programming Models on Intel MIC Computer Cluster 28

Comparison of Parallel Programming Models on Intel MIC Compu...

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28th IEEE international parallel & distributed processing symposium Workshops (IPDPSW)

作者： Lai, Chenggang Hao, Zhijun Huang, Miaoqing Shi, Xuan You, Haihang Univ Arkansas Fayetteville AR 72701 USA Fudan Univ Shanghai Peoples R China Univ Tennessee Knoxville TN 37996 USA

ISBN: (纸本)9781479941162

Coprocessors based on Intel Many Integrated Core (MIC) Architecture have been adopted in many high-performance computer clusters. Typical parallel programming models, such as MPI and OpenMP, are supported on MIC processors to achieve the parallelism. In this work, we conduct a detailed study on the performance and scalability of the MIC processors under different programming models using the Beacon computer cluster. Followings are our findings. (1) The native MPI programming model on the MIC processors is typically better than the offload programming model, which offloads the workload to MIC cores using OpenMP, on Beacon computer cluster. (2) On top of the native MPI programming model, multithreading inside each MPI process can further improve the performance for parallel applications on computer clusters with MIC coprocessors. (3) Given a fixed number of MPI processes, it is a good strategy to schedule these MPI processes to as few MIC processors as possible to reduce the cross-processor communication overhead. (4) The hybrid MPI programming model, in which data processing is distributed to both MIC cores and CPU cores, can outperform the native MPI programming model.

关键词： parallel programming model Intel MIC processor MPI OpenMP performance evaluation

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Proceedings - 2014 22nd Euromicro international Conference on parallel, distributed, and Network-Based processing, PDP 2014

Proceedings - 2014 22nd Euromicro International Conference o...

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2014 22nd Euromicro international Conference on parallel, distributed, and Network-Based processing, PDP 2014

ISBN: (纸本)9781479927289

The proceedings contain 111 papers. The topics discussed include: on partitioning two dimensional finite difference meshes for distributed memory parallel computers;coordinated cooperative work using undependable processors with unreliable broadcast;agricultural reform: more efficient farming using advanced parallel refactoring tools;. the multi-level communication: minimal deadlock-free and storage efficient routing for Torus networks;dynamic feature selection for machine-learning based concurrency regulation in STM;an efficient barrier implementation for OpenMP-like parallelism on the Intel SCC;evaluating the impact of transactional characteristics on the performance of transactional memory applications;scalable parallel I/O on a blue gene/Q supercomputer using compression, topology-aware data aggregation, and subfiling;and EagleMacaw: a dual-tree replication protocol for efficient and reliable P2P media streaming.

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Online Monitoring System for Performance Fault Detection 28

Online Monitoring System for Performance Fault Detection

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28th IEEE international parallel & distributed processing symposium Workshops (IPDPSW)

作者： Gioiosa, Roberto Kestor, Gokcen Kerbyson, Darren J. Pacific Northwest Natl Lab High Performance Comp Richland WA 99354 USA

ISBN: (纸本)9781479941162

To achieve the exaFLOPS performance within a contained power budget, next generation supercomputers will feature hundreds of millions of components operating at low-and near-threshold voltage. As the probability that at least one of these components fails during the execution of an application approaches certainty, it seems unrealistic to expect that any run of a scientific application will not experience some performance faults. We believe that there is need of a new generation of lightweight performance and debugging tools that can be used online even during production runs of parallel applications and that can identify performance anomalies during the application execution. In this work we propose the design and implementation of a monitoring system that continuously inspects the evolution of running applications and the health of the system. To achieve minimum runtime overhead while maintaining the desired level of flexibility, we propose a decoupled approach in which accurate monitoring is performed at kernel-level while performance anomaly disambiguation and corrective actions are performed at user-level. We evaluate our monitoring system on a 32-core AMD Interlagos compute node: First, we show that the runtime overhead of the monitoring system is negligible (0-2%). Then we show how our system can be used to precisely identify performance faults in two different scenarios. In the first, we inject OS noise while in the second we simulate the execution of a data analytics application next to a scientific simulation.

关键词： Exascale Operating system parallel applications Performance faults Reliability

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ABC2: Adaptively balancing computation and communication in a DSM cluster of multicores for irregular applications 28

ABC2: Adaptively balancing computation and communication in ...

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28th IEEE international parallel and distributed processing symposium Workshops, IPDPSW 2014

作者： Koduru, Sai Charan Vora, Keval Gupta, Rajiv Department of Computer Science and Engineering University of California Riverside United States

ISBN: (纸本)9780769552088

Graph-based applications have become increasingly important in many application domains. The large graph sizes offer data level parallelism at a scale that makes it attractive to run such applications on distributed shared memory (DSM) based modern clusters composed of multicore machines. Our analysis of several graph applications that rely on speculative parallelism or asynchronous parallelism shows that the balance between computation and communication differs between applications. In this paper, we study this balance in the context of DSMs and exploit the multiple cores present in modern multicore machines by creating three kinds of threads which allows us to dynamically balance computation and communication: compute threads to exploit data level parallelism in the computation, fetch threads that replicate data into object-stores before it is accessed by compute threads, and update threads that make results computed by compute threads visible to all compute threads by writing them to DSM. We observe that the best configuration for above mechanisms varies across different inputs in addition to the variation across different applications. To this end, we design ABC2: a runtime algorithm that automatically configures the DSM using simple runtime information such as: observed object prefetch and update queue lengths. This runtime algorithm achieves speedups close to that of the best hand-optimized configurations. © 2014 IEEE.

关键词： Graphic methods

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