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22nd ACM international symposium on High-Performance parallel and distributed Computing, HPDC 2013

作者： Su, Yu Agrawal, Gagan Woodring, Jonathan Myers, Kary Wendelberger, Joanne Ahrens, James Computer Science and Engineering Ohio State University Columbus OH 43210 United States Los Alamos National Laboratory Los Alamos NM 87544 United States

ISBN: (纸本)9781450319102

With growing computational capabilities of parallel machines, scientific simulations are being performed at finer spatial and temporal scales, leading to a data explosion. The growing sizes are making it extremely hard to store, manage, disseminate, analyze, and visualize these datasets, especially as neither the memory capacity of parallel machines, memory access speeds, nor disk bandwidths are increasing at the same rate as the computing power. Sampling can be an effective technique to address the above challenges, but it is extremely important to ensure that dataset characteristics are preserved, and the loss of accuracy is within acceptable levels. In this paper, we address the data explosion problems by developing a novel sampling approach, and implementing it in a flexible system that supports server-side sampling and data subsetting. We observe that to allow subsetting over scientific datasets, data repositories are likely to use an indexing technique. Among these techniques, we see that bitmap indexing can not only effectively support subsetting over scientific datasets, but can also help create samples that preserve both value and spatial distributions over scientific datasets. We have developed algorithms for using bitmap indices to sample datasets. We have also shown how only a small amount of additional metadata stored with bitvectors can help assess loss of accuracy with a particular subsampling level. Some of the other properties of this novel approach include: 1) sampling can be flexibly applied to a subset of the original dataset, which may be specified using a value-based and/or a dimension-based subsetting predicate, and 2) no data reorganization is needed, once bitmap indices have been generated. We have extensively evaluated our method with different types of datasets and applications, and demonstrated the effectiveness of our approach. © 2013 ACM.

关键词： Big data

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Hardware MPI-2 functions for multi-processing reconfigurable system on chip

Hardware MPI-2 functions for multi-processing reconfigurable...

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2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Gamom Ngounou Ewo, Roland Christian Kiegaing, Emmanuel Mbouenda, Martin Fotsin, Hilaire Bertrand Granado, Bertrand Laboratoire EEAT LIP6 Université de Douala Douala Cameroon Laboratoire EEAT Université de Douala Douala Cameroon Département de Physique Université de Dschang Dschang Cameroon Laboratoire LIP6 Université de Pierre et Marie Curie Paris France

ISBN: (纸本)9780769549798

In this paper we describe a hardware implementation, of the MPI-2 RMA communication library primitive, devoted to a distributed Multi processing Reconfigurable System on Chip (MP-RSoC). We designed a platform able to process communications over a custom heterogeneous MP-RSoC using our hardware MPI-2 RMA communication primitives. To implement these primitives, we have conceived a scalable Network on Chip based on a crossbar. MPI-2 RMA primitives are directly usable in hardware tasks in the MP-RSoC to transfer data between all resources, either hardware or software. We also show that using message passing for parallel programming can have benefits in term of scalability and heterogeneity. Our hardware primitives have been implemented and tested on Xilinx FPGA spartan6 board. © 2013 IEEE.

关键词： Network-on-chip

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distributed query processing in an ad-hoc semantic web data sharing system

Distributed query processing in an ad-hoc semantic web data ...

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2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Zhou, Jing Bochmann, Gregor V. Shi, Zhongzhi School of Computer Science Communication University of China Beijing China School of Electrical Engineering and Computer Science University of Ottawa ON Canada Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769549798

Sharing the Semantic Web data in proprietary datasets in which data is encoded in RDF triples in a decentralized environment calls for efficient support from distributed computing technologies. The highly dynamic ad-hoc settings that would be pervasive for Semantic Web data sharing among personal users in the future, however, pose even more demanding challenges for the enabling technologies. We extend previous work on a hybrid P2P architecture for an ad-hoc Semantic Web data sharing system which better models the data sharing scenario by allowing data to be maintained by its own providers and exhibits satisfactory scalability owing to the adoption of a two-level distributed index and hashing techniques. Additionally, we propose efficient distributed processing of SPARQL queries in such a context and explore optimization techniques that build upon distributed query processing for database systems and relational algebra optimization. We anticipate that our work will become an indispensable, complementary approach to making the Semantic Web a reality by delivering efficient data sharing and reusing in an ad-hoc environment. © 2013 IEEE.

关键词： Query processing

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Tolerating packet losses in wireless mesh networks

Tolerating packet losses in wireless mesh networks

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2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Engelhardt, Frank Lindhorst, Timo Nett, Edgar University of Magdeburg Institute for Distributed Systems Universiẗatsplatz 2 39106 Magdeburg Germany

ISBN: (纸本)9780769549798

Wireless Mesh Networks (WMNs) provide a promising foundation for a flexible and reliable communication infrastructure in industrial environments. Meeting the QoS demands of real-time applications, though, requires the deployment of various advanced mechanisms. Compared to wired networks, applications face higher packet loss rates in wireless networks due to the inherent unreliability of wireless communication. Furthermore, if mobile stations are involved, links that fail due to node movement frequently cause packet losses. In this paper, we present an approach to tolerate those specific losses by locally recovering lost packets and transiently re-routing them over an alternative path. The evaluation in real-world experiments shows that we can completely prevent packet loss without significantly increasing the end-to-end latency. This allows the deployment of WMNs for real-time applications without explicitly considering the increased error-proneness of wireless communication and station mobility. © 2013 IEEE.

关键词： Packet loss

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2Q*: an effective, low-overhead, improved replacement algorithm for mail service applications in storage system

2Q*: an effective, low-overhead, improved replacement algori...

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IEEE international symposium on parallel and distributed processing with applications (ISPA)

作者： Si, Chengxiang Meng, Xiaoxuan Xu, Lu Coordinat Ctr China Natl Comp Network Emergency Response Tech Team Beijing Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China

Any one algorithm cannot be effective for all applications;therefore, choosing one appropriate for one special application is very meaningful. In this article, we analyzed access patterns for mail service application, and acquired an algorithm appropriate for it. Moreover, based on analysis of performance characteristics for the current algorithm, we proposed an improved algorithm, called 2Q*, which behaves better than others for a full range of sizes. We also verify the effectiveness of 2Q* in a real buffer system, and join it with the main stream pre-fetch policy. The experimental results show that 2Q* can improve IO performance of mail service application effectively.

关键词： cache replacement algorithms mail service

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High performance adaptive distributed scheduling algorithm

High performance adaptive distributed scheduling algorithm

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2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Narang, Ankur Srivastava, Abhinav Shyamasundar, R.K. IBM India Research Laboratory New Delhi India Laboratoire DInformatique de Grenoble Grenoble France Tata Institute of Fundamental Research Mumbai India

ISBN: (纸本)9780769549798

Exascale computing requires complex runtime systems that need to consider affinity, load balancing and low time and message complexity for scheduling massive scale parallel computations. Simultaneous consideration of these objectives makes online distributed scheduling a very challenging problem. Prior distributed scheduling approaches are limited to shared memory or primarily use work-stealing across distributed memory nodes for load-balancing or depend on the programmer specified affinity. However, the performance of affinity driven scheduling and work stealing based algorithms degrades when the input is irregular(UTS) and/or sparse. In this paper we present a novel adaptive distributed scheduling algorithm (ALDS) for multi-place parallel computations, that uses a unique combination of remote (inter-place) spawns and remote work steals to reduce the overheads in the scheduler, which helps to dynamically maintain load balance across the compute nodes of the system, while ensuring affinity maximally. Using parallel machine learning algorithms such as Support Vector Regression running concurrently with program execution on the target architecture, ALDS can automatically and adaptively tune the parameters for scalable performance. Our design was implemented using GASNet API and POSIX threads. For the UTS (Unbalanced Tree Search) benchmark (using up to 2048 nodes of Blue Gene/P), we deliver superior performance over Charm++ [1] and [2]. © 2013 IEEE.

关键词： Scheduling

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Virtual SoC: A full-system simulation environment for massively parallel heterogeneous system-on-chip

Virtual SoC: A full-system simulation environment for massiv...

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2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Bortolotti, Daniele Pinto, Christian Marongiu, Andrea Ruggiero, Martino Benini, Luca DEI-University of Bologna Viale Risorgimento 2 40136 Bologna Italy

ISBN: (纸本)9780769549798

Driven by flexibility, performance and cost constraints of demanding modern applications, heterogeneous System-on-Chip (SoC) is the dominant design paradigm in the embedded system computing domain. SoC architecture and heterogeneity clearly provide a wider power/performance scaling, combining high performance and power efficient general-purpose cores along with massively parallel many-core-based accelerators. Besides the complex hardware, generally these kinds of platforms host also an advanced software ecosystem, composed by an operating system, several communication protocol stacks, and various computational demanding user applications. The necessity to efficiently cope with the hugeHW/SW design space provided by this scenario makes clearly full-system simulator one of the most important design tools. We present in this paper a new emulation framework, called Virtual SoC, targeting the full-system simulation of massively parallel heterogeneous SoCs. © 2013 IEEE.

关键词： System-on-chip

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Reducing the cost of measuring memory hierarchy communication parameters

Reducing the cost of measuring memory hierarchy communicatio...

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2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Jiang, Feng Sussman, Alan Department of Computer Science George Washington University 801 22nd Street NW Washington DC 20052 United States UMIACS Department of Computer Science University of Maryland College Park MD 20742 United States

ISBN: (纸本)9780769549798

For parallelizing compilers that target multi-core machines, some hardware information is very useful in producing optimized code. One approach to obtain such information is extracting the characteristics of the hardware from a set of performance data collected by performing extensive measurements on the computer system. However, such measurements tend to be heavy-weight and time-consuming, which makes them unable to complete in a reasonable amount of time, especially on a large-scale system. We propose an algorithm to minimize the required measurements on a computer system using the tree structure of the memory hierarchy, that divides resources into equivalence classes so that different members of an equivalence class do not require separate measurements. Correctness arguments for the algorithms are presented, along with results that show the effectiveness and performance of the algorithms. © 2013 IEEE.

关键词： Equivalence classes

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HadoopCL: MapReduce on distributed heterogeneous platforms through seamless integration of hadoop and OpenCL

HadoopCL: MapReduce on distributed heterogeneous platforms t...

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2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Grossman, Max Breternitz, Mauricio Sarkar, Vivek Department of Computer Science Rice University United States AMD United States

ISBN: (纸本)9780769549798

As the scale of high performance computing systems grows, three main challenges arise: the programmability, reliability, and energy efficiency of those systems. Accomplishing all three without sacrificing performance requires a rethinking of legacy distributed programming models and homogeneous clusters. In this work, we integrate Hadoop MapReduce with OpenCL to enable the use of heterogeneous processors in a distributed system. We do this by exploiting the implicit data parallelism of mappers and reducers in a MapReduce system. Combining Hadoop and OpenCL provides 1) an easy-to-learn and flexible application programming interface in a high level and popular programming language, 2) the reliability guarantees and distributed file system of Hadoop, and 3) the low power consumption and performance acceleration of heterogeneous processors. This paper presents HadoopCL: an extension to Hadoop which supports execution of user-written Java kernels on heterogeneous devices, optimizes communication through asynchronous transfers and dedicated I/O threads, automatically generates OpenCL kernels from Java byte code using the open source tool APARAPI, and achieves nearly 3x overall speedup and better than 55x speedup of the computational sections for example MapReduce applications, relative to Hadoop. © 2013 IEEE.

关键词： MapReduce

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V2X: An automated tool for building SystemC-based simulation environments in designing multicore systems-on-chips

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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 2013年第1期36卷 48-62页

作者： Hung, Shih-Hao Tu, Chia-Heng Liaw, Yuh-Hung Natl Taiwan Univ Grad Inst Networking & Multimedia Taipei 106 Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei 106 Taiwan

Simulation methodologies have been widely utilized to aid hardware/software co-design and shorten the development cycles of systems-on-chips (SoCs). For a complex multicore system, traditional hardware description languages (HDLs), such as Verilog and VHDL, consume too much time in a simulation and are far too slow to perform parallel programs and modern operating systems. Instead, SystemC provides a higher-level environment to reduce the simulation time and is often a better choice for hardware/software co-design. For existing HDL-based chip designs, it is possible to automatically convert them to SystemC or even higher-level functional descriptions to improve the simulation speed and enable hardware/software co-design. However, existing tools failed to accomplish that for a complex multicore SoC, such as the OpenSPARC T1. Therefore, we investigated the problems encountered by two most popular converting tools, Verilator and V2SC, and developed our own tool, called V2X, to overcome the problems. In our case study, V2X successfully translated the 8-core OpenSPARC T1 SoC (approximately 300,000 lines of Verilog code) into SystemC and significantly reduced the simulation time by 40 times for the user. In addition, this article discusses the two-stage translation scheme which makes V2X more powerful than existing tools and the quick replay method for automatic generation of chip verification suites for the new SystemC-based simulation.

关键词： multicore Verilog to SystemC translator system-level simulation

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