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Unstructured control flow in GPGPU

Unstructured control flow in GPGPU

引用

2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Dominguez, Rodrigo Kaeli, David R. Department of Electrical and Computer Engineering Northeastern University Boston United States

ISBN: (纸本)9780769549798

The current trend toward heterogeneous architectures motivates us to reconsider current software and hardware paradigms. The focus is centered around new parallel programming models, compiler design, and runtime resource management techniques to exploit the features of many-core processor architectures. Graphics processing Units (GPU) have become the platform of choice in this area for accelerating a large range of data-parallel and task-parallel applications. The rapid adoption of GPU computing has been greatly aided by the introduction of high-level programming environments such as CUDA C and OpenCL. However, each vendor implements these programming models differently and we must analyze the internals in order to get a better understanding of the performance results. One of the main differences across implementations is the handling of program control flow by the compiler and the hardware. Some implementations can support unstructured control flow based on branches and labels;others are based on structured control flow relying solely on if-Then and while constructs. In this paper we describe a tool that can be used to analyze the difference between these two approaches. We created a dynamic compiler called Caracal that translates applications with unstructured control flow so they can run on hardware that requires structured programs. In order to accomplish this, Caracal builds a control tree of the program and creates single-entry, single-exit regions called hammock graphs. We used this tool to analyze the performance differences between NVIDIA's implementation of CUDA C and AMD'simplementation of OpenCL. We found that the requirement for structured control flow can increase the number of registers allocated by 20 registers and impact performance as much as2x. © 2013 IEEE.

关键词： Graphics processing unit

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Visualizing parallelism in CS 2

Visualizing parallelism in CS 2

引用

2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Massung, Sean Heeren, Cinda Computer Science Dept College of Engineering University of Illinois Urbana-Champaign United States

ISBN: (纸本)9780769549798

This paper describes the incorporation of the IEEE-TCPP Curriculum Initiative into CS 2 at the University of Illinois at Urbana-Champaign. With control over only one course that requires a semi-rigid curriculum, we detail a sequence of three lessons that explore the basics of parallelism in a visual manner. We draw a contrast between standard teaching methods for parallelism and assert that our approach is more engaging and more accessible, particularly to spatial learners. We then present examples of our image-centric course material and discuss its deployment. Lastly, we reflect on the effectiveness of this technique over the past two semesters and consider its direction in the future. © 2013 IEEE.

关键词： Curricula

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Efficient network packet signature matching on GPUs

Efficient network packet signature matching on GPUs

引用

international symposium on Instrumentation & Measurement, Sensor Network and Automation (IMSNA)

作者： Xiaohui Pan Modern Education Technology Center Shanghai University of Political Science and Law Shanghai China

Network signature matching is an important task in many applications such as network security or traffic analysis, which generally rely on a flexible signature matching system to extract important packet information from each processed packet. This task is computation and data intensive, and requires significant processing time in sequential manner. In order to accelerate signature matching of giga-bit network traffic, we aim to exploit the inherent parallelism of signature matching through the use of parallel graphics processor units. In this paper, we present detailed analysis of signature matching along with the system design for parallel graphics processors(GPUs). The signature matching schema proposed is based on port matching and keyword matching in each packet header. A real system on graphics processor units was implemented to evaluate the efficacy of our design. Experimental results proved that signature matching can be efficiently done on graphics processor units.

关键词： Graphics processing units Protocols Matched filters Classification algorithms Information filters Automata

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Portable memory consistency for software managed distributed memory in many-core SoC

Portable memory consistency for software managed distributed...

引用

2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Rutgers, Jochem H. Bekooij, Marco J.G. Smit, Gerard J.M. University of Twente Department of EEMCS P.O. Box 217 7500 AE Enschede Netherlands

ISBN: (纸本)9780769549798

Porting software to different platforms can require modifications of the application. One of the issues is that the targeted hardware supports another memory consistency model. As a consequence, the completion order of reads and writes in a multi-threaded application can change, which may result in improper synchronization. For example, a processor with out-of-order execution could break synchronization if proper fence instructions are missing. Such a bug can cause sporadic errors, which are hard to debug. This paper presents an approach that makes applications independent of the memory model of the hardware, hence they can be compiled to hardware with any memory architecture. The key is having a memory model that only guarantees the most fundamental orderings of reads and writes, and annotations to specify additional ordering constraints. As a result, tooling can transparently and properly implement fences, cache flushes, etc. when appropriate, without losing flexibility of the hardware design. In a case study, several SPLASH-2 applications are run on a 32-core software cache coherent Micro Blaze system in FPGA. Moreover, this approach also allows mapping to scratch-pad memories and a distributed shared memory architecture. © 2013 IEEE.

关键词： Fences

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A multi-level optimization method for stencil computation on the domain that is bigger than memory capacity of GPU

A multi-level optimization method for stencil computation on...

引用

2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Jin, Guanghao Endo, Toshio Matsuoka, Satoshi Tokyo Institute of Technology JST-CREST Tokyo Japan Tokyo Institute of Technology NII JST-CREST Tokyo Japan

ISBN: (纸本)9780769549798

The problem size of the stencil computation on GPU is limited by the GPU memory capacity, which is typically smaller than that of host memory. This paper proposes and evaluates a multi-level optimization method for stencil computation to achieve both larger problem size than GPU memory and high performance. It is based on the temporal blocking method, which has been proposed to improve memory access locality of stencil computation. It applies temporal blocking to 2 layers to improve locality of computation. Then it reuses former result to solve redundant problem. Furthermore, it parallels computation with communication by 2 additional buffers. Evaluation of 7-point stencil simulation on 3D domain shows that our new method achieves 16.74 times better performance than naive method and 1.35 times better performance than other methods on average. © 2013 IEEE.

关键词： Graphics processing unit

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High performance GPU accelerated local optimization in TSP

High performance GPU accelerated local optimization in TSP

引用

2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Rocki, Kamil Suda, Reiji University of Tokyo Graduate School of Information Science and Technology Department of Computer Science 7-3-1 Hongo Bunkyo-ku Tokyo Japan

ISBN: (纸本)9780769549798

This paper presents a high performance GPU accelerated implementation of 2-opt local search algorithm for the Traveling Salesman Problem (TSP). GPU usage significantly decreases the execution time needed for tour optimization, however it also requires a complicated and well tuned implementation. With the problem size growing, the time spent on local optimization comparing the graph edges grows significantly. According to our results based on the instances from the TSPLIB library, the time needed to perform a simple local search operation can be decreased approximately 5 to 45 times compared to a corresponding parallel CPU code implementation using 6 cores. The code has been implemented in OpenCL and as well as in CUDA and tested on AMD and NVIDIA devices. The experimental studies show that the optimization algorithm using the GPU local search converges from up to 300 times faster compared to the sequential CPU version on average, depending on the problem size. The main contributions of this paper are the problem division scheme exploiting data locality which allows to solve arbitrarily big problem instances using GPU and the parallel implementation of the algorithm itself. © 2013 IEEE.

关键词： parallel architectures

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The DFrame:parallel programming using a distributed framework implemented in MPI

The DFrame:Parallel programming using a distributed framewor...

引用

The 12th international symposium on distributed Computing and applications to Business,Engineering and Science(DCABES 2013)(第十二届分布式计算及其应用国际学术研讨会)

作者： Tony Mclay Andreas Hoppe Darrel R Greenhill Souheil Khaddaj Faculty of Computing Information Systems and MathematicsKingston UniversityLondonKTI 2EEUK

High content throughput imaging systems must apply time consuming complex image processing algorithms to multiple bio-medical image *** systems are typically designed to use parallel resources in order to achieve results in reasonable time *** paper presents the design of a distributed framework that provides separation of the largely orthogonal parallelisation from the domain image processing algorithm *** allows reuse and pluggable extension of parallelising patterns,as well as providing for extensibility of domain image processing.

关键词： component distributed computing,mpi,image processing

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Tightly coupled accelerators architecture for minimizing communication latency among accelerators

Tightly coupled accelerators architecture for minimizing com...

引用

2013 IEEE 37th Annual Computer Software and applications Conference, COMPSAC 2013

作者： Hanawa, Toshihiro Kodama, Yuetsu Boku, Taisuke Sato, Mitsuhisa Center for Computational Sciences University of Tsukuba 1-1-1 Tennodai Tsukuba Ibaraki 305-8577 Japan

ISBN: (纸本)9780769549798

In recent years, heterogeneous clusters using accelerators have been widely used in high performance computing systems. In such clusters, inter-node communication among accelerators requires several memory copies via CPU memory, and the communication latency causes severe performance degradation. In order to address this problem, we propose the Tightly Coupled Accelerators (TCA) architecture to reduce the communication latency between accelerators over different nodes. In addition, we promote the HA-PACS project at the Center for Computational Sciences, University of Tsukuba, in order to build up the HA-PACS base cluster system, as a commodity GPU cluster, and to develop an experimental system based on the TCA architecture as a proprietary interconnection network connecting accelerators beyond the nodes. In the present paper, we describe the TCA architecture and the design and implementation of PEACH2 for realizing the TCA architecture. We also evaluate the functionality and the basic performance of the PEACH2 chip, and the results demonstrate that the PEACH2 chip has sufficient maximum performance with 93% of the theoretical peak performance and a latency between adjacent nodes of approximately 0.8usec. © 2013 IEEE.

关键词： Graphics processing unit

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Pattern-Direct and Layout-Aware Replication Scheme for parallel I/O Systems

Pattern-Direct and Layout-Aware Replication Scheme for Paral...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： Yanlong Yin Jibing Li Jun He Xian-He Sun Rajeev Thakur Computer Science Department Illinois Institute of Technology Chicago IL USA Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA

ISBN: (纸本)9781467360661

The performance gap between computing power and the I/O system is ever increasing, and in the meantime more and more High Performance Computing (HPC) applications are becoming data intensive. This study describes an I/O data replication scheme, named Pattern-Direct and Layout-Aware (PDLA) data replication scheme, to alleviate this performance gap. The basic idea of PDLA is replicating identified data access pattern, and saving these reorganized replications with optimized data layouts based on access cost analysis. A runtime system is designed and developed to integrate the PDLA replication scheme and existing parallel I/O system; a prototype of PDLA is implemented under the MPICH2 and PVFS2 environments. Experimental results show that PDLA is effective in improving data access performance of parallel I/O systems.

关键词： Layout Optimization Runtime Data models Prototypes System analysis and design Computational modeling

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Tolerating Packet Losses in Wireless Mesh Networks

Tolerating Packet Losses in Wireless Mesh Networks

引用

IEEE international symposium on parallel and distributed processing Workshops and PhD Forum

作者： Frank Engelhardt Timo Lindhorst Edgar Nett University of Magdeburg Institute for Distributed Systems

ISBN: (纸本)9781479913725

Wireless Mesh Networks (WMNs) provide a promising foundation for a flexible and reliable communication infrastructure in industrial environments. Meeting the QoS demands of real-time applications, though, requires the deployment of various advanced mechanisms. Compared to wired networks, applications face higher packet loss rates in wireless networks due to the inherent unreliability of wireless communication. Furthermore, if mobile stations are involved, links that fail due to node movement frequently cause packet losses. In this paper, we present an approach to tolerate those specific losses by locally recovering lost packets and transiently re-routing them over an alternative path. The evaluation in real-world experiments shows that we can completely prevent packet loss without significantly increasing the end-to-end latency. This allows the deployment of WMNs for real-time applications without explicitly considering the increased error-proneness of wireless communication and station mobility.

关键词： Packet loss Wireless mesh networks real-time application program CARRIER SYSTEM deployment Communications infrastructure factory environment mobile station end-to-end Wireless networks network applications Quality of service

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