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Using Static Code Analysis to Improve Performance of GridRPC applications

Using Static Code Analysis to Improve Performance of GridRPC...

26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Girko, Oleg Lastovetsky, Alexey Univ Coll Dublin Sch Comp Sci & Informat Dublin 2 Ireland

ISBN: (纸本)9780769546766

The paper presents an approach to improve performance of GridRPC applications by statically analysing dynamic workflows. An extension to GridRPC API is used to specify the region of code to apply static code analysis to, during the compilation phase. The information collected is then used at runtime for building a graph of dependencies between tasks, which is analysed to assign servers to tasks in an optimal way, minimising the time of computation and communication. This approach handles branching and looping correctly by building an extended dependency graph, which covers all branches of the code. \ The experimental results are provided to show that in many practically important cases this approach leads to better results than individual mapping of tasks or run-time task discovery.

关键词： Grid GridRPC task mapping task scheduling workflows mapping

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Improved Bioinformatics processing Unit for Multiple applications

Improved Bioinformatics Processing Unit for Multiple Applica...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Liu, Pei Hemani, Ahmed Paul, Kolin Royal Inst Technol KTH Dept Elect Syst Sch ICT Stockholm Sweden IIT Dept Comp Sci & Engn New Delhi India

ISBN: (纸本)9780769546766

This paper presents a coarse-grain reconfigurable unit for accelerating multiple widely used bioinformatics algorithms. Our design is a highly efficient, programmable bioinformatics processing unit, called BiCell v2. Based on a specialized multimode multiplier, this unit provides three different working modes, in order to accelerate four popular bioinformatics algorithms: Maximum Likelihood based phylogenetic inference, Needleman-Wunsch, Smith-Waterman, and HMMER in sequence alignment. BiCell v2 supports both single and double precision floating-point computation, which significantly increases the accuracy for bioinformatics algorithm acceleration but retains silicon area efficiency. Making use of this improved processing unit, our platform gives about 10X speedup compared to our previous design in single-precision, and 23.2X speedup comparing with GPGPU in the same precision.

关键词： component Bioinformatics Coarse-Grained Reconfigurable Architecture Phylogenetic Inference Needleman-Wunsch Smith- Waterman HMMER Maximum-Likelihood VLSI

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Fault Tolerance in P2P-Grid Environments

Fault Tolerance in P2P-Grid Environments

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Wang, Huan Hidenori, Nakazato Waseda Univ Grad Sch Global Informat & Telecommun Studies Tokyo Japan

ISBN: (纸本)9780769546766

P2P-Grid system provides a framework for converging Grid and peer-to-peer network to deploy large-scale distributed applications. However, working nodes with heterogeneous properties can freely join and leave in the middle of their computation. The nodes dynamic participation arbitrarily at any time according to user's decision can keep changing the topology of the network and also causing more common execution failures than in other systems. To this end, failure detection mechanisms and fault tolerance function typically as an integral part of P2P-Grid system have been well-studied. Our research aims to address the highly dynamic nature that arises in P2P-Grid systems by understanding nodes life time statistics in previous research. We are proposing a Checkpointing-and-Recovery architecture for applications restarting as soon as possible on P2P-Grid systems. And failure-detection mechanism is a necessary prerequisite to fault tolerance and fault recovery in P2P-Grid system. We also investigate how the design of various failure detection algorithms affects their performance in node average failure detection time. The evaluation shows our checkpointing and restart paradigm and failure detection algorithm enables high reliability and performance with high node departure.

关键词： P2P-Grid fault tolerance failure detection failure recovery

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Modeling and Predicting Performance of High Performance Computing applications on Hardware Accelerators

Modeling and Predicting Performance of High Performance Comp...

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26th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Meswani, Mitesh R. Carrington, Laura Unat, Didem Snavely, Allan Baden, Scott Poole, Stephen UCSD SDSC La Jolla CA USA

ISBN: (纸本)9780769546766

Computers with hardware accelerators, also referred to as hybrid-core systems, speedup applications by offloading certain compute operations that can run faster on accelerators. Thus, it is not surprising that many of top500 supercomputers use accelerators. However, in addition to procurement cost, significant programming and porting effort is required to realize the potential benefit of such accelerators. Hence, before building such a system it is prudent to answer the question 'what is the projected performance benefit from accelerators for the workloads of interest?'. We address this question by way of a performance-modeling framework that predicts realizable application performance on accelerators rapidly and accurately without going to the considerable effort of porting and tuning. The modeling framework first automatically identifies commonly found compute patterns in scientific applications which we term idioms, which may benefit by accelerator technology. Next the framework models the predicted speedup of those idioms if they were to be ported to and run on hardware accelerators. As a proof of concept we characterize two kinds of accelerators 1) the FPGA accelerators on a Convey HC-1 system and 2) an NVIDIA FERMI GPU accelerator. We model performance of the idioms gather/scatter and stream and our predictions show that where these occur in two full-scale HPC applications, Milc and HYCOM, gather/scatter speeds up by as much as 15X, and stream by as much as 14X, whereas the overall compute time of Milc improves by 3.4% and HYCOM by 20%.

关键词： accelerators GPU FPGA performance prediction performance modeling benchmarking HPC

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Static Power Optimization for Homogeneous Multiple GPUs Based on Task Partition

Static Power Optimization for Homogeneous Multiple GPUs Base...

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2nd international Congress on Computer applications and Computational Science (CACS 2011)

作者： Lin, Yisong Tang, Tao Wang, Guibin National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9783642283079;9783642283086

Recently, GPU has been widely used in High Performance Computing (HPC). In order to improve computational performance, several GPUs are integrated into one computer node in practical system. However, power consumption of GPUs is very high and becomes as bottleneck to its further development. In doing so, optimizing power consumption have been draw broad attention in the research area and industry community. In this paper, we present an energy optimization model considering performance constraint for homogeneous multi-GPUs, and propose a performance prediction model when task partitioning policy is specified. Experiment results validate that the model can accurately predict the execution of program for single or multiple GPUs, and thus reduce static power consumption by the guide of task partition.

关键词： Electric power utilization

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V2X: An automated tool for building SystemC-based simulation environments in designing multicore systems-on-chips

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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 2013年第1期36卷 48-62页

作者： Hung, Shih-Hao Tu, Chia-Heng Liaw, Yuh-Hung Natl Taiwan Univ Grad Inst Networking & Multimedia Taipei 106 Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei 106 Taiwan

Simulation methodologies have been widely utilized to aid hardware/software co-design and shorten the development cycles of systems-on-chips (SoCs). For a complex multicore system, traditional hardware description languages (HDLs), such as Verilog and VHDL, consume too much time in a simulation and are far too slow to perform parallel programs and modern operating systems. Instead, SystemC provides a higher-level environment to reduce the simulation time and is often a better choice for hardware/software co-design. For existing HDL-based chip designs, it is possible to automatically convert them to SystemC or even higher-level functional descriptions to improve the simulation speed and enable hardware/software co-design. However, existing tools failed to accomplish that for a complex multicore SoC, such as the OpenSPARC T1. Therefore, we investigated the problems encountered by two most popular converting tools, Verilator and V2SC, and developed our own tool, called V2X, to overcome the problems. In our case study, V2X successfully translated the 8-core OpenSPARC T1 SoC (approximately 300,000 lines of Verilog code) into SystemC and significantly reduced the simulation time by 40 times for the user. In addition, this article discusses the two-stage translation scheme which makes V2X more powerful than existing tools and the quick replay method for automatic generation of chip verification suites for the new SystemC-based simulation.

关键词： multicore Verilog to SystemC translator system-level simulation

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Performance Benefits of Heterogeneous Computing in HPC Workloads

Performance Benefits of Heterogeneous Computing in HPC Workl...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Lee, Victor W. Grochowski, Ed Geva, Robert Intel Corp Santa Clara CA 95054 USA

ISBN: (纸本)9780769546766

Chip multi-processors (CMPs) with increasing number of processor cores are now becoming widely available. To take advantage of many-core CMPs, applications must be parallelized. However, due to the nature of algorithm / programming model, some parts of the application would remain serial. According to Amdahl's law, the speedup of a parallel application is limited by the amount of serial execution it has. For a CMP with many cores, this can be a serious limitation. To take full advantage of the increasing number of cores, one must try to reduce the execution time of the serial portion of a parallel program. However, rewriting an application takes time and often the return on the effort invested may not justify parallelizing every part of the program. Heterogeneous many-core CMP design is one possible solution to support massive parallel execution and to provide a reasonable single-thread performance. In this paper, we use a simple spreadsheet model to evaluate homogeneous and heterogeneous CMP designs using execution profiles of real HPC applications. Evaluated on 12 parallel HPC applications, we show that heterogeneous CMPs can outperform homogeneous CMPs by up to 1.35x with an average speedup of 1.06x when both the heterogeneous CMPs and homogeneous CMPs are constrained to use the same power budget. Our study found the heterogeneous CMPs can take advantage of serial portion of execution that is as little as 2% of total run time to provide performance benefit. This suggests heterogeneous computing can help mitigate the effect of not parallelizing some portions of an application due to return on investment concern on programming efforts.

关键词： Chip multi-processors (CMPs) HPC parallel programs heterogeneous computing

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Meteor Shower: A Reliable Stream processing System for Commodity Data Centers

Meteor Shower: A Reliable Stream Processing System for Commo...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Wang, Huayong Peh, Li-Shiuan Koukoumidis, Emmanouil Tao, Shao Chan, Mun Choon MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA Natl Univ Singapore Sch Comp Singapore Singapore

ISBN: (纸本)9780769546759

Large-scale failures are commonplace in commodity data centers, the major platforms for distributed Stream processing Systems (DSPSs). Yet, most DSPSs can only handle single-node failures. Here, we propose Meteor Shower, a new fault-tolerant DSPS that overcomes large-scale burst failures while improving overall performance. Meteor Shower is based on checkpoints. Unlike previous schemes, Meteor Shower orchestrates operators' checkpointing activities through tokens. The tokens originate from source operators, trickle down the stream graph, triggering each operator that receives these tokens to checkpoint its own state1. Meteor Shower is a suite of three new techniques: 1) source preservation, 2) parallel, asynchronous checkpointing, and 3) application-aware checkpointing. Source preservation allows Meteor Shower to avoid the overhead of redundant tuple saving in prior schemes;parallel, asynchronous checkpointing enables Meter Shower operators to continue processing streams during a checkpoint;while application-aware checkpointing lets Meteor Shower learn the changing pattern of operators' state size and initiate checkpoints only when the state size is minimal. All three techniques together enable Meteor Shower to improve throughput by 226% and lower latency by 57% vs prior state-of-the-art. Our results were measured on a prototype implementation running three real world applications in the Amazon EC2 Cloud.

关键词： stream computing fault tolerance reliability

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RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture for Signal processing on FPGAs

RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Hillenbrand, Dominic Brugger, Christian Tao, Jie Yang, Shufan Balzer, Matthias Karlsruhe Inst Technol D-76021 Karlsruhe Germany Hunan Univ Sch Comp & Commun Embedded Syst Networking Lab Changsha 410082 Hunan Peoples R China

ISBN: (纸本)9780769546766

We present a scalable run-time configurable and programmable signal processing architecture for real-time applications which covers a wide performance spectrum. Our approach goes beyond conventional special purpose signal processing engines. Scalability has multiple dimensions: on core-and network-level. We base our novel architecture on programmable components which can be re-combined and re-configured to match application specific requirements for signal processing tasks at run-time. Users of the RIVER architecture can use our pre-synthesized cores to avoid HDL-coding and lengthy FPGA translation. For evaluation we have mapped computational-and memory-intensive kernels to the RIVER architecture and achieved 250 GMACs which is significantly (1.6-2x) more than many high-end DSPs provide.

关键词： signal processing Field programmable gate arrays ARCHITECTURE Building construction Custom design real-time application program configurability Runtime PROGRAMMABLE

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processing Dependent Tasks on a Heterogeneous GPU Resource Architecture

Processing Dependent Tasks on a Heterogeneous GPU Resource A...

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2nd IEEE international Conference on parallel, distributed and Grid Computing (PDGC)

作者： Yang, Rui Thomas, Johnson Oklahoma State Univ Stillwater OK 74078 USA

ISBN: (纸本)9781467329255;9781467329224

The development of General Purpose GPUs (GPGPU) provides multiple cores of computing power and high memory bandwidth that can meet the high performance requirements of researchers in diverse areas such as weather forecasting, bioinformatics, and even nuclear simulation. In this work we present a Heterogeneous GPU computing system (HG) which can utilize GPUs with different capabilities. Firstly, the HG quantifies the capability of each GPU, and then assigns an acceptable workload to each GPU. The HG is different from other distributed GPU systems because HG can process dependent tasks which indicates the tasks in HG can communicate with each other. Using this architecture HG can deal with more complex task dependent applications. To validate our approach, in the first set of experiments we show that multiple GPU performs better in complex computing applications. Next we use 2D heat equation application to compare HG with a MPI program running on CPUs. With increasing work set size, computing power of HG results in a much better performance than the CPUs system.

关键词： heterogeneous GPU multiple GPUs dependent tasks

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