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Efficient On-line Hardware/Software Task Scheduling For Dynamic Run-time Reconfigurable Systems

Efficient On-line Hardware/Software Task Scheduling For Dyna...

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26th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Al-Wattar, Ahmed Areibi, Shawki Saffih, Faycal School of Engineering University of Guelph Guelph ON N1G 2W1 Canada

ISBN: (纸本)9780769546766

Modern reconfigurable devices such as FPGAs can be reconfigured at run time. Some of them can be dynamically partially reconfigured, which means part of the FPGA is changed without interrupting other parts. This feature adds tremendous flexibility to the Reconfigurable Computing (RC) Field but also introduces challenges. Reconfigurable Operating Systems tend to ease applications development and most importantly applications verifications and maintenance. In this paper we propose novel scheduling algorithms for reconfigurable computing that can handle both hardware and software tasks. The algorithms proposed reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software/hardware, and give priority to hardware tasks. Results obtained indicate that adding a software processor element not only adds flexibility, but also increases system performance. Two on-line schedulers were designed and implemented. RCSched-I is a simple based implementation that nominates the first available free Partial Reconfigurable Region (PRR) for new tasks. RCSched-II on the other hand nominates any free PRR. Both schedulers check the nominated PRR(s) against the ready task for a match, then decide if there is a need for reconfiguration or not. RCSched-II reconfigures the least recently configured PRR, which increases hardware tasks reuse and decreases total processing time.

关键词： Reconfigurable Computing Reconfigurable OS Partial Reconfiguration Scheduling Hardware tasks Hardware OS Task Migration

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HydEE: Failure Containment without Event Logging for Large Scale Send-Deterministic MPI applications

HydEE: Failure Containment without Event Logging for Large S...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Guermouche, Amina Ropars, Thomas Snir, Marc Cappello, Franck INRIA Saclay Ile France F-91405 Orsay France Ecole Polytech Fed Lausanne Lausanne Switzerland Univ Illinois Urbana IL 60680 USA

ISBN: (纸本)9780769546759

High performance computing will probably reach exascale in this decade. At this scale, mean time between failures is expected to be a few hours. Existing fault tolerant protocols for message passing applications will not be efficient anymore since they either require a global restart after a failure (checkpointing protocols) or result in huge memory occupation (message logging). Hybrid fault tolerant protocols overcome these limits by dividing applications processes into clusters and applying a different protocol within and between clusters. Combining coordinated checkpointing inside the clusters and message logging for the inter-cluster messages allows confining the consequences of a failure to a single cluster, while logging only a subset of the messages. However, in existing hybrid protocols, event logging is required for all application messages to ensure a correct execution after a failure. This can significantly impair failure free performance. In this paper, we propose HydEE, a hybrid rollback-recovery protocol for send-deterministic message passing applications, that provides failure containment without logging any event, and only a subset of the application messages. We prove that HydEE can handle multiple concurrent failures by relying on the send-deterministic execution model. Experimental evaluations of our implementation of HydEE in the MPICH2 library show that it introduces almost no overhead on failure free execution.

关键词： High performance computing MPI fault tolerance send-determinism failure containment

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A discussion in favor of Dynamic Scheduling for regular applications in Many-core Architectures

A discussion in favor of Dynamic Scheduling for regular appl...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Garcia, Elkin Orozco, Daniel Pavel, Robert Gao, Guang R. Univ Delaware Dept Elect & Comp Engn Comp Architecture & Parallel Syst Lab Newark DE 19716 USA

ISBN: (纸本)9780769546766

The recent evolution of many-core architectures has resulted in chips where the number of processor elements (PEs) are in the hundreds and continue to increase every day. In addition, many-core processors are more and more frequently characterized by the diversity of their resources and the way the sharing of those resources is arbitrated. On such machines, task scheduling is of paramount importance to orchestrate a satisfactory distribution of tasks with an efficient utilization of resources, especially when fine-grain parallelism is desired or required. In the past, the primary focus of scheduling techniques has been on achieving load balancing and reducing overhead with the aim to increase total performance. This focus has resulted in a scheduling paradigm where Static Scheduling (SS) is preferred to Dynamic Scheduling (DS) for highly regular and embarrassingly parallel applications running on homogeneous architectures. We have revisited the task scheduling problem for these types of applications under the scenario imposed by many-core architectures to investigate whether or not there exists scenarios where DS is better than SS. Our main contribution is the idea that, for highly regular and embarrassingly parallel applications, DS is preferable to SS in some situations commonly found in many-core architectures. We present experimental evidence that shows how the performance of SS is degraded by the new environment on many-core chips. We analyze three reasons that contribute to the superiority of DS over SS on many-core architectures under the situations described: 1) A uniform mapping of work to processors without considering the granularity of tasks is not necessarily scalable under limited amounts of work. 2) The presence of shared resources (i.e. the crossbar switch) produces unexpected and stochastic variations on the duration of tasks that SS is unable to manage properly. 3) Hardware features, such as in-memory atomic operations, greatly contribute to decrea

关键词： core construction dynamic scheduling ARCHITECTURE TASK SCHEDULING Resource utilization Religious Missions PROCESSOR cross-bar switch Regular

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Enhancing the scalability of consistency-based progressive multiple sequences alignment applications

Enhancing the scalability of consistency-based progressive m...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Orobitg, M. Cores, F. Guirado, F. Kemena, C. Notredame, C. Ripoll, A. Univ Lleida Dept Comp Sci Lleida Spain Univ Pompeu Fabra Ctr Genom Regulat Barcelona Spain Univ Autonoma Barcelona Comp Architecture & Operating Syst Bellaterra Spain

ISBN: (纸本)9780769546759

Multiple Sequence Alignment (MSA) is an extremely powerful tool for important biological applications, such as phylogenetic analysis, identification of conserved motifs and domains and structure prediction. In this paper we propose a new approach to reduce the computational requirements of T-Coffee, a memory demanding MSA tool that uses a consistency-based scheme to produce more accurate alignments. Our goal is to minimize the memory constraints in order to increase the performance and scalability of the application. The experimental results show that our approach is able to reduce the memory consumption and increase both the time performance and the number and the length of sequences that the method can align. In summary, it is able to reduce the memory requirements by between 72% and 58% depending on the optimization level, improving the alignment scalability as a whole. Also, the library reduction yields a further improvement: the alignment execution time can be reduced by up to 92%. These results are obtained without a significant impact on the final alignment quality, that declines by less than 3%.

关键词： Multiple sequence alignment scalability T-Coffee

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Strengthened Iterated Hill Cipher for Encrypted processing

Strengthened Iterated Hill Cipher for Encrypted Processing

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2nd IEEE international Conference on parallel, distributed and Grid Computing (PDGC)

作者： Haridas, Deepthi Venkataraman, Sarma Varadan, Geeta Govt India Dept Space Adv Data Proc Res Inst ADRIN Secunderabad 500009 Andhra Pradesh India

ISBN: (纸本)9781467329255;9781467329224

Majority of the homomorphic encryption schemes which are been used in many applications are asymmetric, required for the third party processing of encrypted data. Hardly few symmetric homomorphic schemes been proposed, most of them have been cracked. The Iterated Hill Cipher (IHC) is an additive symmetric homomorphic scheme. A novel generalized recurrence has been introduced for IHC in this work. The novelty of the Iterated Hill Cipher (IHC) of the present implementation lies on the fact that every time the cipher is invoked for processing of encrypted data, a random quasigroup along with a different initialization vector are generated dynamically. The existing IHC is based on an arbitrary matrix, which might cause a successful cryptanalytic attack on IHC. Almost all ciphers based on quasigroups consider a scenario where the quasi group (which forms the part of key) to be used for encryption and decryption are pre determined. As a measure to strengthen the existing IHC the present work chooses the matrix to be a dynamically generated random latin square (no storage requirement of quasigroup), the method is illustrated to construct the latin square. The novelty of the present work lies on the fact that it elaborates the criteria of varying key parameters in a specified manner which enables the cipher to still retain its property to be used for encrypted processing as well as upgrading the cipher to a probabilistic cipher.

关键词： cryptography statistical analysis

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Load Balancing of Dynamical Nucleation Theory Monte Carlo Simulations Through Resource Sharing Barriers

Load Balancing of Dynamical Nucleation Theory Monte Carlo Si...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Arafat, Humayun Sadayappan, P. Dinan, James Krishnamoorthy, Sriram Windus, Theresa L. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Argonne Natl Lab Math & Comp Sci Div Argonne IL 60439 USA Pacific Northwest Natl Lab Comp Sci & Math Div Richland WA 99354 USA Iowa State Univ Dept Chem Ames IA 50011 USA

ISBN: (纸本)9780769546759

The dynamical nucleation theory Monte Carlo (DNTMC) application from the NWChem computational chemistry suite utilizes a Markov chain Monte Carlo, two-level parallel structure, with periodic synchronization points that assemble the results of independent finer-grained calculations. Like many such applications, the existing code employs a static partitioning of processes into groups and assigns each group a piece of the finer-grained parallel calculation. A significant cause of performance degradation is load imbalance among groups since the time requirements of the inner-parallel calculation varies widely with the input problem and as a result of the Monte Carlo simulation. We present a novel approach to load balancing such calculations with minimal changes to the application. We introduce the concept of a resource sharing barrier (RSB) - a barrier that allows process groups waiting on other processes' work to actively contribute to their completion. The RSB load balancing technique is applied to the production DNTMC application code, resulting in a small code change of 200 lines and a reduction in execution time of up to 37%.

关键词： Monte Carlo Simulation parallel processing Load balancing Resource management Global Arrays PGAS

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Low-Cost parallel Algorithms for 2:1 Octree Balance

Low-Cost Parallel Algorithms for 2:1 Octree Balance

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Isaac, Tobin Burstedde, Carsten Ghattas, Omar Univ Texas Austin Inst Computat Engn & Sci ICES Austin TX 78712 USA

ISBN: (纸本)9780769546759

The logical structure of a forest of octrees can be used to create scalable algorithms for parallel adaptive mesh refinement (AMR), which has recently been demonstrated for several petascale applications. Among various frequently used octree-based mesh operations, including refinement, coarsening, partitioning, and enumerating nodes, ensuring a 2:1 size balance between neighboring elements has historically been the most expensive in terms of CPU time and communication volume. The 2:1 balance operation is thus a primary target to optimize. One important component of a parallel balance algorithm is the ability to determine whether any two given octants have a consistent distance/size relation. Based on new logical concepts we propose fast algorithms for making this decision for all types of 2: 1 balance conditions in 2D and 3D. Since we are able to achieve this without constructing any parent nodes in the tree that would otherwise need to be sorted and communicated, we can significantly reduce the required memory and communication volume. In addition, we propose a lightweight collective algorithm for reversing the asymmetric communication pattern induced by non-local octant interactions. We have implemented our improvements as part of the open-source "p4est" software. Benchmarking this code with both synthetic and simulation-driven adapted meshes we are able to demonstrate much reduced runtime and excellent weak and strong scalability. On our largest benchmark problem with 5.13 x 10(11) octants the new 2:1 balance algorithm executes in less than 8 seconds on 112,128 CPU cores of the Jaguar Cray XT5 supercomputer.

关键词： Octrees Adaptive mesh refinement parallel algorithms Scientific computing High performance computing

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Exploration of Automatic Optimization for CUDA Programming

Exploration of Automatic Optimization for CUDA Programming

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2nd IEEE international Conference on parallel, distributed and Grid Computing (PDGC)

作者： Al-Mouhamed, Mayez Khan, Ayaz ul Hassan King Fahd Univ Petr & Minerals Dhahran 31261 Saudi Arabia

ISBN: (纸本)9781467329255;9781467329224

Graphic processing Units (GPUs) are gaining ground in high-performance computing. CUDA (an extension to C) is most widely used parallel programming framework for general purpose GPU computations. However, the task of writing optimized CUDA program is complex even for experts. We present a method for restructuring loops into an optimized CUDA kernels based on a 3-step algorithm which are loop tiling, coalesced memory access, and resource optimization. We also establish the relationships between the influencing parameters and propose a method for finding possible tiling solutions with coalesced memory access that best meets the identified constraints. We also present a simplified algorithm for restructuring loops and rewrite them as an efficient CUDA Kernel. The execution model of synthesized kernel consists of uniformly distributing the kernel threads to keep all cores busy while transferring a tailored data locality which is accessed using coalesced pattern to amortize the long latency of the secondary memory. In the evaluation, we implement some simple applications using the proposed restructuring strategy and evaluate the performance in terms of execution time and GPU throughput.

关键词： CUDA GPU parallel Programming Compiler Transformations directive-based language source-to-source compiler GPGPU

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BLOR: Bandwidth and Latency Sensitive Overlay Routing for Flash Data Dissemination

BLOR: Bandwidth and Latency Sensitive Overlay Routing for Fl...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Li, Xiaoyong Wang, Yijie Fu, Yongquan Li, Xiaoling Sun, Weidong Natl Univ Def Technol Sch Comp Sci Natl Lab Parallel & Distributed Proc Changsha Hunan Peoples R China

ISBN: (纸本)9780769546766

Flash data dissemination transmits time-critical data to distributed receivers in a timely manner, which is widely used in many mission-critical applications. However, existing flash data dissemination approaches fail to guarantee the timely transmission due to the unpredictability of the dissemination process. Overlay routing has been widely used as an efficient routing primitive for providing better end-to-end routing quality, based on detouring inefficient routing paths in the P2P network. To improve the predictability of the flash data dissemination process, we propose a bandwidth and latency sensitive overlay routing scheme BLOR, by optimizing the overlay routing and avoiding poor performance of the data dissemination paths. BLOR tries to select optimal paths in terms of latency, bandwidth capacity and available bandwidth in nature, which has never been studied before. Additionally, a location-aware unstructured overlay topology construction scheme is proposed to improve the routing efficiency and data location, as well as an unbiased top-k dominating model is proposed to balance the multi-factor choosing for path selecting, in the optimization process of BLOR. Experimental results with real-world data sets confirm that BLOR significantly improves flash data dissemination.

关键词： data dissemination overlay topology construction routing path selection

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Optimal Resource Rental Planning for Elastic applications in Cloud Market

Optimal Resource Rental Planning for Elastic Applications in...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Zhao, Han Pan, Miao Liu, Xinxin Li, Xiaolin Fang, Yuguang Univ Florida Dept Comp & Informat Sci & Engn Gainesville FL 32611 USA Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9780769546759

This paper studies the optimization problem of minimizing resource rental cost for running elastic applications in cloud while meeting application service requirements. Such a problem arises when excessive generated data incurs significant monetary cost on transfer and inventory in cloud. The goal of planning is to make resource rental decisions in response to varying application progress in the most cost-effective way. To address this problem, we first develop a Deterministic Resource Rental Planning (DRRP) model, using a mixed integer linear program, to generate optimal rental decisions given fixed cost parameters. Next, we systematically analyze the predictability of the time-varying spot instance prices in Amazon EC2 and find that the best achievable prediction is insufficient to provide a close approximation to the actual prices. This fact motivates us to propose a Stochastic Resource Rental Planning (SRRP) model that explicitly considers the price uncertainty in rental decision making. Using empirical spot price data sets and realistic cost parameters, we conduct simulations over a wide range of experimental scenarios. Results show that DRRP achieves as much as 50% cost reduction compared to the no-planning scheme. Moreover, SRRP consistently outperforms its DRRP counterpart in terms of cost saving, which demonstrates that SRRP is highly adaptive to the unpredictable nature of spot price in cloud resource market.

关键词： Cloud Computing Amazon EC2 Spot Instance Resource Rental Planning Stochastic Optimization

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