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Augmentation of Programs with CUDA Streams

Augmentation of Programs with CUDA Streams

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international symposium on parallel and distributed processing with applications, ISPA

作者： Sharmistha Madhur Amilkanthwar Shankar Balachandran Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai India

A program that is run on a General Purpose Graphics processing Unit (GPGPU) has to stall if the data is not resident in the GPGPU. With CUDA 2.0 architecture, data can be streamed while the computation is still on. Exploiting this feature requires careful orchestration of data transfer and computation which typically requires a significant effort from the programmer. We propose an approach of transforming C programs to programs that can make use of CUDA streams. We identify the regions where data transfer and computation can be overlapped by using a polyhedral framework called PLUTO[2]. We use the PLUTO framework to do automatic tiling of source code and use the streaming capabilities to overlap data transfer with computation. Our results show an average speedup of 1.5X over CUDA programs without streaming optimizations.

关键词： Graphics processing unit Kernel Pluto Tiles Optimization parallel processing

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High throughput compression of floating point numbers on graphical processing units

High throughput compression of floating point numbers on gra...

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international Conference on parallel distributed and Grid Computing (PDGC)

作者： Ajith Padyana C. D. Sudheer Pallav Kumar Baruah Ashok Srinivasan Department of Mathematics and Computer Science Sri Sathya Sai Institute of Higher Learning Puttaparthi India Department of Computer Science Florida State University Tallahassee FL USA

Compute-intensive tasks in high-end high performance computing (HPC) systems often generate large amounts of data, especially floating-point data, that need to be transmitted over the network. Although computation speeds are very high, the overall performance of these applications is affected by the data transfer overhead. Moreover, as data sets are growing in size rapidly, bandwidth limitations pose a serious bottleneck in several scientific applications. Fast floating point compression can ameliorate the bandwidth limitations. If data is compressed well, then the amount of data transfer is reduced. This reduction in data transfer time comes at the expense of the increased computation required by compression and decompression. It is important for compression and decompression rates to be greater than the network bandwidth; otherwise, it will be faster to transmit uncompressed data directly. Accelerators such as Graphics processing Units (GPU) provide much computational power. In this paper, we show that the computational power of GPUs can be harnessed to provide sufficiently fast compression and decompression for this approach to be effective for data produced by many practical applications. In particularly, we use Holt's Exponential smoothing algorithm from time series analysis, and encode the difference between its predictions and the actual data. This yields a lossless compression scheme. We show that it can be implemented efficiently on GPUs to provide an effective compression scheme for the purpose of saving on data transfer overheads. The primary contribution of this work lies in demonstrating the potential of floating point compression in reducing the I/O bandwidth bottleneck on modern hardware for important classes of scientific applications.

关键词： Lead

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Towards Cross Stratum SLA Management with the GEYSERS Architecture

Towards Cross Stratum SLA Management with the GEYSERS Archit...

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international symposium on parallel and distributed processing with applications, ISPA

作者： Alexandru-Florian Antonescu Philip Robinson Luis Miguel Contreras-Murillo José Aznar Sébastien Soudan Fabienne Anhalt Joan A. García-Espín SAP Research Zurich Switzerland SAP Research Belfast U.K Lyatiss Lyon France Telefónica I+D Madrid Spain Telefónica ID Madrid Spain i2CAT Foundation Barcelona Spain

The objectives of Cross Stratum Optimization (CSO) and SLA Management in multi-domain infrastructure services lead to challenges for maintaining autonomy of resource control and coordination of the SLA lifecycle. The GEYSERS project includes an approach and architecture for SLA Management to address these two problems. The conceptual foundations and blueprint of this architecture are presented and assessed.

关键词： Computer architecture Control systems Protocols Complexity theory Quality of service Resource management

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L2 Cache Performance Analysis and Optimizations for processing HDF5 Data on Multi-core Nodes

L2 Cache Performance Analysis and Optimizations for Processi...

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international symposium on parallel and distributed processing with applications, ISPA

作者： Rajdeep Bhowmik Madhusudhan Govindaraju Grid and Cloud Computing Research Laboratory Department of Computer Science SUNY at Binghamton Binghamton NY USA

It is important to design and develop scientific middleware libraries to harness the opportunities presented by emerging multi-core processors that are available on grid and cloud environments. Scientific middleware libraries not adhering or adapting to this programming paradigm can suffer from severe performance limitations while executing on emerging multi-core processors. In this paper, we focus on the utilization of a critical shared resource on chip multiprocessors (CMPs), the L2 cache. The way in which an application schedules and assigns processing work to each thread determines the access pattern of the shared L2 cache, which may result in either enhancing or diminishing the effects of memory latency on a multi-core processor. Therefore, while processing scientific datasets such as HDF5, it is essential to conduct fine-grained analysis of cache utilization, to make informed processing and scheduling decisions in multi-threaded programming. In this paper, using the TAU toolkit for performance feedback from dual- and quad-core machines, we analyze and recommend methods for effective scheduling of threads on multi-core nodes to augment the performance of scientific applications processing HDF5 data. We discuss the benefits that can be achieved by using L2 Cache-Affinity and L2 Balanced-Set based scheduling algorithms for improving L2 cache performance and effectively the overall execution time.

关键词： Instruction sets Multicore processing Optimization Processor scheduling Hardware Libraries Middleware

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A Self-stabilizing Algorithm for the Maximal 2-packing in a Cactus Graph

A Self-stabilizing Algorithm for the Maximal 2-packing in a ...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Joel Antonio Trejo-S'nchez José Alberto Fern'ndez-Zepeda Universidad del Caribe Cancun Quintana Roo MX Centro de Investigacion Cientifica y de Educacion Superior de Ensenada Ensenada Baja California MX

In this paper we present a time optimal self-stabilizing algorithm for the maximal 2-packing in a cactus graph. The cactus is a network topology such that any edge belongs to at most one cycle. The cactus has important applications in telecommunication networks, location problems, biotechnology, among others. The execution time of this algorithm is proportional to the diameter of the cactus. To the best of our knowledge, this algorithm outperforms current algorithms presented in the literature for this problem and in this topology.

关键词： Algorithm design and analysis Nominations and elections Color Topology Heuristic algorithms Hafnium Boolean functions

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A Generic VHDL Template for 2D Stencil Code applications on FPGAs

A Generic VHDL Template for 2D Stencil Code Applications on ...

引用

IEEE international symposium on Object/Component/Service-Oriented Real-Time distributed Computing Workshops (ISORCW)

作者： Michael Schmidt Marc Reichenbach Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Erlangen-Nuremberg Germany

The efficient realization of self-organizing systems based on 2D stencil code applications, like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive and also computational-intensive, because often a high number of iterations is required. FPGAs are predestined for the realization of these algorithms. They are very flexible, allow a scalable parallel processing and have a moderate power consumption, even in high-performance versions. Therefore, FPGAs are highly qualified to make these applications also real-time capable. Our goal was to implement an efficient parameterizable buffering and parallel processing scheme for such operations in FPGAs, to process them as fast as possible. We developed a generic VHDL template which allows a scalable parallelization and pipelining of 2D stencil code applications in relation to application and hardware constraints.

关键词： Computer architecture Microprocessors Field programmable gate arrays Pipeline processing Clocks Bandwidth Real time systems

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Energy Efficiency Analysis of GPUs

Energy Efficiency Analysis of GPUs

引用

IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Juan M. Cebri'n Ginés D. Guerrero José M. García Computer Engineering Deptartment University of Murcia Murcia Spain

In the last few years, Graphics processing Units (GPUs) have become a great tool for massively parallel computing. GPUs are specifically designed for throughput and face several design challenges, specially what is known as the Power and Memory Walls. In these devices, available resources should be used to enhance performance and throughput, as the performance per watt is really high. For massively parallel applications or kernels, using the available silicon resources for power management was unproductive, as the main objective of the unit was to execute the kernel as fast as possible. However, not all the applications that are being currently ported to GPUs can make use of all the available resources, either due to data dependencies, bandwidth requirements, legacy software on new hardware, etc, reducing the performance per watt. This new scenario requires new designs and optimizations to make these GPGPU's more energy efficient. But first comes first, we should begin by analyzing the applications we are running on these processors looking for bottlenecks and opportunities to optimize for energy efficiency. In this paper we analyze some kernels taken from the CUDA SDK 2 in order to discover resource underutilization. Results show that this underutilization is present, and resource optimization can increase the energy efficiency of GPU-based computation. We then discuss different strategies and proposals to increase energy efficiency in future GPU designs.

关键词： Graphics processing unit Kernel Bandwidth Power dissipation Benchmark testing Clocks Hardware

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The SPAS-UAH Cluster for the JEM-EUSO Computing Model

The SPAS-UAH Cluster for the JEM-EUSO Computing Model

引用

international symposium on parallel and distributed processing with applications, ISPA

作者： J.A. Morales de los Ríos G. Sáez-Cano H. Prieto L. del Peral J.H. Carretero K. Shinozaki M.D. Rodríguez-Frías SPace & AStroparticle (SPAS) Group UAH Madrid Spain RIKEN 2-1 Hirosawa Wako Saitama Japan

The JEM-EUSO space observatory will be launched and attached to the Japanese module of the international Space Station (ISS) in 2016. Its aims is to observe UV photon tracks produced by Ultra High Energy Cosmic Rays (UHECR) and Extremely High Energy Cosmic Rays (EHECR) developing in the atmosphere and producing Extensive Air Showers (EAS). JEM-EUSO will use our atmosphere as a huge calorimeter, to detect the electromagnetic and hadronic components of the EAS. For High Energy Physic (HEP) experiments the huge amount of data and complex analysis algorithms require the use of advanced GRID computational resources. Therefore a complete infrastructure is needed for the simulation and data analysis, in the frame of the GRID architecture, and computing infrastructure, intended for the JEM-EUSO space mission software. Moreover solutions to account for a complete installed cluster system, with the software and data repositories, as well as a many other details are pointed out.

关键词： Atmospheric modeling Software Data analysis Linux Data models Analytical models Terrestrial atmosphere

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Improved Bioinformatics processing Unit for Multiple applications

Improved Bioinformatics Processing Unit for Multiple Applica...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Pei Liu Ahmed Hemani Kolin Paul Department of Electronic System School of ICT KTH Royal Institute of Technology Stockholm Sweden Department of Computer Science and engineering Indian Institute of Technology New Delhi India

This paper presents a coarse-grain reconfigurable unit for accelerating multiple widely used bioinformatics algorithms. Our design is a highly efficient, programmable bioinformatics processing unit, called BiCell v2. Based on a specialized multimode multiplier, this unit provides three different working modes, in order to accelerate four popular bioinformatics algorithms: Maximum Likelihood based phylogenetic inference, Needleman-Wunsch, Smith-Waterman, and HMMER in sequence alignment. BiCell v2 supports both single and double precision floating-point computation, which significantly increases the accuracy for bioinformatics algorithm acceleration but retains silicon area efficiency. Making use of this improved processing unit, our platform gives about 10X speedup compared to our previous design in single-precision, and 23.2X speedup comparing with GPGPU in the same precision.

关键词： Bioinformatics Phylogeny Adders Silicon Arrays Acceleration

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RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture for Signal processing on FPGAs

RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Dominic Hillenbrand Christian Brugger Jie Tao Shufan Yang Matthias Balzer KIT - Karlsruhe Institute of Technology Germany Hunan University School of Computer and Communication Embedded System and Networking Laboratory

We present a scalable run-time configurable and programmable signal processing architecture for real-time applications which covers a wide performance spectrum. Our approach goes beyond conventional special purpose signal processing engines. Scalability has multiple dimensions: on core- and network-level. We base our novel architecture on programmable components which can be re-combined and re-configured to match application specific requirements for signal processing tasks at run-time. Users of the RIVER architecture can use our pre-synthesized cores to avoid HDL-coding and lengthy FPGA translation. For evaluation we have mapped computational- and memory-intensive kernels to the RIVER architecture and achieved 250 GMACs which is significantly (1.6-2x) more than many high-end DSPs provide.

关键词： Field programmable gate arrays Computer architecture Signal processing Streaming media Rivers Real time systems Embedded systems

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