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Dalorex: A Data-Local Program Execution and Architecture for Memory-bound applications 29

Dalorex: A Data-Local Program Execution and Architecture for...

引用

29th IEEE international symposium on High-Performance Computer Architecture (HPCA)

作者： Orenes-Vera, Marcelo Tureci, Esin Wentzlaff, David Martonosi, Margaret Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781665476522

applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching, decoupling, or pipelining can mitigate memory latency and improve core utilization, memory bottlenecks persist due to limited off-chip bandwidth. Approaches doing processing in-memory (PIM) with Hybrid Memory Cube (HMC) overcome bandwidth limitations but fail to achieve high core utilization due to poor task scheduling and synchronization overheads. Moreover, the high memory-per-core ratio available with HMC limits strong scaling. We introduce Dalorex, a hardware-software co-design that achieves high parallelism and energy efficiency, demonstrating strong scaling with >16,000 cores when processing graph and sparse linear algebra workloads. Over the prior work in PIM, both using 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing tile holds an equal amount of data, and all memory operations are local;(2) a task-based parallel programming model where tasks are executed by the processing unit that is co-located with the target data;(3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata;(4) novel traffic-aware task scheduling hardware that maintains high core utilization;and (5) a data-placement strategy that improves work balance. This work proposes architectural and software innovations to provide the greatest scalability to date for running graph algorithms while still being programmable for other domains.

关键词： distributed scalable parallel data-local near-memory architecture sparse graph NoC network bandwidth

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DECISION: Distributing OpenVX applications on CPUs, GPUs and FPGAs using OpenCL 36

DECISION: Distributing OpenVX Applications on CPUs, GPUs and...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Kalms, Lester Haering, Tim Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9781665497473

The demand for computer vision systems and algorithms is steadily increasing. However, users often have to deal with different or new languages, architectures and tools. Furthermore, there is often no linkage between vendors, defined standards, or model-based modularization to connect everything. We propose a modularized framework for distributing applications on heterogeneous systems consisting of CPUs, GPUs, and FPGAs. The user builds an OpenVX-compliant application without knowledge of the underlying hardware. The middleend automatically schedules and maps the nodes to the available OpenCL devices. Benefits of FPGA acceleration, such as pipelining and running multiple nodes in parallel, are taken into account. The backend generates a program including memory management, synchronization mechanisms and data transfers, even between vendors. This is executed in our parallelized OpenCL based runtime system with minimal overhead. We achieved speedups of 1.63 for a heterogeneous schedule in comparison to a single GPU design when limiting the FPGA resources. Without this limitation a speedup of 13.39 is achieved for the same application.

关键词： OpenVX OpenCL Framework Scheduling Mapping Computer Vision FPGA GPU CPU

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PARSIR: a Package for Effective parallel Discrete Event Simulation on Multi-processor Machines 28

PARSIR: a Package for Effective Parallel Discrete Event Simu...

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28th IEEE/ACM international symposium on distributed Simulation and Real Time applications, DS-RT 2024

作者： Quaglia, Francesco DICII - University of Rome Tor Vergata Italy

ISBN: (纸本)9798331527211

In this article we present PARSIR (parallel SImulation Runner), a package that enables the effective exploitation of shared-memory multi-processor machines for running discrete event simulation models. PARSIR is a compile/run-time environment for discrete event simulation models developed with the C programming language. The architecture of PARSIR has been designed in order to keep low the amount of CPU-cycles required for running models. This is achieved via the combination of a set of techniques like: 1) causally consistent batch-processing of simulation events at an individual simulation object for caching effectiveness;2) high likelihood of disjoint access parallelism;3) the favoring of memory accesses on local NUMA (Non-Uniform-Memory-Access) nodes in the architecture, while still enabling well balanced workload distribution via work-stealing from remote nodes;4) the use of RMW (Read-Modify-Write) machine instructions for fast access to simulation engine data required by the worker threads for managing the concurrent simulation objects and distributing the workload. Furthermore, any architectural solution embedded in the PARSIR engine is fully transparent to the application level code implementing the simulation model. We also provide experimental results showing the effectiveness of PARSIR when running the reference PHOLD benchmark on a NUMA shared-memory multi-processor machine equipped with 40 CPUs. © 2024 IEEE.

关键词： Batch data processing

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A General Offloading Approach for Near-DRAM processing-In-Memory Architectures 36

A General Offloading Approach for Near-DRAM Processing-In-Me...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Chen, Dan Jin, Hai Zheng, Long Huang, Yu Yao, Pengcheng Gui, Chuangyi Wang, Qinggang Liu, Haifeng He, Haiheng Liao, Xiaofei Zheng, Ran Huazhong Univ Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Serv Comp Technol & Syst Lab Clusters & Grid Comp Lab Wuhan Peoples R China

ISBN: (纸本)9781665481069

processing-in-memory (PIM) is promising to solve the well-known data movement challenge by performing in-situ computations near the data. Leveraging PIM features is pretty profitable to boost the energy efficiency of applications. Early studies mainly focus on improving the programmability for computation offloading on PIM architectures. They lack a comprehensive analysis of computation locality and hence fail to accelerate a wide variety of applications. In this paper, we present a general-purpose instruction-level offloading technique for near-DRAM PIM architectures, namely IOTPIM, to exploit PIM features comprehensively. IOTPIM is novel with two technical advances: 1) a new instruction offloading policy that fully considers the locality of the whole on-chip cache hierarchy, and 2) an offloading performance benefit prediction model that directly predicts offloading performance benefits of an instruction based on the input dataset characterizes, preserving low analysis overheads. The evaluation demonstrates that IOTPIM can be applied to accelerate a wide variety of applications, including graph processing, machine learning, and image processing. IOTPIM outperforms the state-of-the-art PIM offloading techniques by 1.28x-1.51x while ensuring offloading accuracy as high as 91.89% on average.

关键词： processing-in-memory PIM offloading technique data locality

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parallel Algorithms for Adding a Collection of Sparse Matrices 36

Parallel Algorithms for Adding a Collection of Sparse Matric...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Hussain, Md Taufique Abhishek, Guttu Sai Buluc, Aydin Azad, Ariful Indiana Univ Bloomington IN 47405 USA Indian Inst Technol Mumbai Maharashtra India Lawrence Berkeley Natl Lab Berkeley CA USA

ISBN: (纸本)9781665497473

We develop a family of parallel algorithms for the SpKAdd operation that adds a collection of k sparse matrices. SpKAdd is a much needed operation in many applications including distributed memory sparse matrix-matrix multiplication (SpGEMM), streaming accumulations of graphs, and algorithmic sparsification of the gradient updates in deep learning. While adding two sparse matrices is a common operation in Matlab, Python, Intel MKL, and various GraphBLAS libraries, these implementations do not perform well when adding a large collection of sparse matrices. We develop a series of algorithms using tree merging, heap, sparse accumulator, hash table, and sliding hash table data structures. Among them, hash-based algorithms attain the theoretical lower bounds both on the computational and I/O complexities and perform the best in practice. The newly-developed hash SpKAdd makes the computation of a distributed-memory SpGEMM algorithm at least 2x faster than previous state-of-the-art algorithms.

关键词： Deep learning distributed processing Instruction sets Merging Memory management Data structures Libraries

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Generalized Flow-Graph Programming Using Template Task-Graphs: Initial Implementation and Assessment 36

Generalized Flow-Graph Programming Using Template Task-Graph...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Schuchart, Joseph Nookala, Poornima Javanmard, Mohammad Mahdi Herault, Thomas Valeev, Edward F. Bosilca, George Harrison, Robert J. Univ Tennessee Innovat Comp Lab Knoxville TN 37996 USA SUNY Stony Brook Inst Adv Computat Sci Stony Brook NY 11794 USA Meta Platforms Inc New York NY USA Virginia Polytech Inst & State Univ Dept Chem Blacksburg VA 24061 USA

ISBN: (纸本)9781665481069

We present and evaluate TTG, a novel programming model and its C++ implementation that by marrying the ideas of control and data flowgraph programming supports compact specification and efficient distributed execution of dynamic and irregular applications. Programming interfaces that support taskbased execution often only support shared memory parallel environments;a few support distributed memory environments, either by discovering the entire DAG of tasks on all processes, or by introducing explicit communications. The first approach limits scalability, while the second increases the complexity of programming. We demonstrate how TTG can address these issues without sacrificing scalability or programmability by providing higher-level abstractions than conventionally provided by taskcentric programming systems, without impeding the ability of these runtimes to manage task creation and execution as well as data and resource management efficiently. TTG supports distributed memory execution over 2 different task runtimes, PaRSEC and MADNESS. Performance of four paradigmatic applications (in graph analytics, dense and block-sparse linear algebra, and numerical integrodifferential calculus) with various degrees of irregularity implemented in TTG is illustrated on large distributed-memory platforms and compared to the state-of-theart implementations.

关键词： Hybrid programming techniques in applications

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Shared-Memory parallel Algorithms for Fully Dynamic Maintenance of 2-Connected Components 36

Shared-Memory Parallel Algorithms for Fully Dynamic Maintena...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Haryan, Chirayu Anant Ramakrishna, G. Kothapalli, Kishore Banerjee, Dip Sankar Indian Inst Technol Tirupati Tirupati Andhra Pradesh India Int Inst Informat Technol Hyderabad Hyderabad India Indian Inst Technol Jodhpur Jodhpur Rajasthan India

ISBN: (纸本)9781665481069

Finding the biconnected components of a graph has a large number of applications in many other graph problems including planarity testing, computing the centrality metrics, finding the (weighted) vertex cover, coloring, and the like. Recent years saw the design of efficient algorithms for this problem across sequential and parallel computational models. However, current algorithms do not work in the setting where the underlying graph changes over time in a dynamic manner via the insertion or deletion of edges. the insertion or deletion of edges. Dynamic algorithms in the sequential setting that obtain the biconnected components of a graph upon insertion or deletion of a single edge are known from over two decades ago. parallel algorithms for this problem are not heavily studied. In this paper, we design shared-memory parallel algorithms that obtain the biconnected components of a graph subsequent to the insertion or deletion of a batch of edges. Our algorithms hence will be capable of exploiting the parallelism adduced due to a batch of updates. We implement our algorithms on an AMD EPYC 7742 CPU having 128 cores. Our experiments on a collection of 10 realworld graphs from multiple classes indicate that our algorithms outperform parallel state-of-the-art static algorithms.

关键词： Semiconductor device modeling Measurement distributed processing Heuristic algorithms Instruction sets Computational modeling Maintenance engineering

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2nd Workshop on Composable Systems (COMPSYS 2023)

2023 IEEE International Parallel and Distributed Processing ...

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2023 IEEE international parallel and distributed processing symposium Workshops, IPDPSW 2023 2023年 939-940页

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High-order Line Graphs of Non-uniform Hypergraphs: Algorithms, applications, and Experimental Analysis 36

High-order Line Graphs of Non-uniform Hypergraphs: Algorithm...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Liu, Xu T. Firoz, Jesun Aksoy, Sinan Amburg, Ilya Lumsdaine, Andrew Joslyn, Cliff Praggastis, Brenda Gebremedhin, Assefaw H. Univ Washington Seattle WA 98195 USA Washington State Univ Pullman WA 99164 USA Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781665481069

Hypergraphs offer flexible and robust data representations for many applications, but methods that work directly on hypergraphs are not readily available and tend to be prohibitively expensive. Much of the current analysis of hypergraphs relies on first performing a graph expansion - either based on the nodes (clique expansion), or on the hyperedges (line graph) - and then running standard graph analytics on the resulting representative graph. However, this approach suffers from massive space complexity and high computational cost with increasing hypergraph size. Here, we present efficient, parallel algorithms to accelerate and reduce the memory footprint of higher-order graph expansions of hypergraphs. Our results focus on the hyperedge-based s-line graph expansion, but the methods we develop work for higher-order clique expansions as well. To the best of our knowledge, ours is the first framework to enable hypergraph spectral analysis of a large dataset on a single sharedmemory machine. Our methods enable the analysis of datasets from many domains that previous graph-expansion-based models are unable to provide. The proposed s-line graph computation algorithms are orders of magnitude faster than state-of-the-art sparse general matrix-matrix multiplication methods, and obtain approximately 2 - 31x speedup over a prior state-of-the-art heuristic-based algorithm for s-line graph computation.

关键词： Hypergraphs parallel hypergraph algorithms line graphs intersection graphs clique expansion

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Kernel Launcher: C++ Library for Optimal-Performance Portable CUDA applications

Kernel Launcher: C++ Library for Optimal-Performance Portabl...

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2023 IEEE international parallel and distributed processing symposium Workshops, IPDPSW 2023

作者： Heldens, Stijn Van Werkhoven, Ben Netherlands EScience Center Amsterdam Netherlands

ISBN: (纸本)9798350311990

Graphic processing Units (GPUs) have become ubiquitous in scientific computing. However, writing efficient GPU kernels can be challenging due to the need for careful code tuning. To automatically explore the kernel optimization space, several auto-tuning tools - like Kernel Tuner - have been proposed. Unfortunately, these existing auto-tuning tools do not concern themselves with integration of tuning results back into applications, which puts a significant implementation and maintenance burden on application developers. In this work, we present Kernel Launcher: an easy-to-use C++ library that simplifies the creation of highly-tuned CUDA applications. With Kernel Launcher, programmers can capture kernel launches, tune the captured kernels for different setups, and integrate the tuning results back into applications using runtime compilation. To showcase the applicability of Kernel Launcher, we consider a real-world computational fluid dynamics code and tune its kernels for different GPUs, input domains, and precisions. © 2023 IEEE.

关键词： Graphics processing unit

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