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Massive streaming data analytics: A case study with clustering coefficients

Massive streaming data analytics: A case study with clusteri...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： David Ediger Karl Jiang Jason Riedy David A. Bader Georgia Institute of Technology Atlanta GA USA

ISBN: (纸本)9781424465330

We present a new approach for parallel massive graph analysis of streaming, temporal data with a dynamic and extensible representation. Handling the constant stream of new data from health care, security, business, and social network applications requires new algorithms and data structures. We examine data structure and algorithm trade-offs that extract the parallelism necessary for high-performance updating analysis of massive graphs. Static analysis kernels often rely on storing input data in a specific structure. Maintaining these structures for each possible kernel with high data rates incurs a significant performance cost. A case study computing clustering coefficients on a general-purpose data structure demonstrates incremental updates can be more efficient than global recomputation. Within this kernel, we compare three methods for dynamically updating local clustering coefficients: a brute-force local recalculation, a sorting algorithm, and our new approximation method using a Bloom filter. On 32 processors of a Cray XMT with a synthetic scale-free graph of 2 24 ¿ 16 million vertices and 2 29 ¿ 537 million edges, the brute-force method processes a mean of over 50 000 updates per second and our Bloom filter approaches 200 000 updates per second.

关键词： Data analysis Clustering algorithms Data structures Kernel Filters Medical services Data security Social network services Data mining parallel processing

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Solving large sparse linear systems in a grid environment using Java

Solving large sparse linear systems in a grid environment us...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Raphaël Couturier Fabienne Jézéquel Laboratoire d Informatique de l Université de Franche-Comté IUT Belfort-Montbéliard Belfort France Laboratoire d'Informatique de Paris 6 UMR 7606 UPMC Universidad Paris 06 Paris France

ISBN: (纸本)9781424465330

In this paper, we show how to solve large sparse linear systems in a grid environment using the Java language and the MPJ library for communication. We describe a parallel version of the GMRES method which takes into account the sparsity of the matrix for message exchanges among processors. Two implementations are compared: one in Java using MPJ and one in C using MPI. The performance of both codes is also compared with that of the PETSc library. Experiments have been carried out using the GRID'5000 platform, on the one hand, on a local cluster, and, on the other hand, on clusters located in distant geographical sites. It is noticeable that the performance of our solver in Java is comparable to the same solver written in C and also to the PETSc library. Our solver in Java allowed us to solve sparse systems of size up to 2 billions with two geographically distant sites.

关键词： Linear systems Java Libraries Sparse matrices Grid computing Large-scale systems Switches Iterative methods Message passing Computer applications

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Acceleration of spiking neural networks in emerging multi-core and GPU architectures

Acceleration of spiking neural networks in emerging multi-co...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Mohammad A. Bhuiyan Vivek K. Pallipuram Melissa C. Smith Tarek Taha Rommel Jalasutram Department of Electrical and Computer Engineering Clemson University Clemson USA

Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabilities. Among various spiking neuron models, the Hodgkin-Huxley model is the oldest and most compute intensive, whereas the more recent Izhikevich model is very compute efficient. Some of the recent multi-core processors and accelerators including Graphical processing Units, IBM's Cell Broadband Engine, AMD Opteron, and Intel Xeon can take advantage of task and thread level parallelism, making them good candidates for large-scale SNN simulations. In this paper we implement and analyze two character recognition networks based on these spiking neuron models. We investigate the performance improvement and optimization techniques for SNNs on these accelerators over an equivalent software implementation on a 2.66 GHz Intel Core 2 Quad. We report significant speedups of the two SNNs on these architectures. It has been observed that given proper application of optimization techniques, the commodity X86 processors are viable options for those applications that require a nominal amount of flops/byte. But for applications with a significant number of flops/byte, specialized architectures such as GPUs and cell processors can provide better performance. Our results show that a proper match of architecture with algorithm complexity provides the best performance.

关键词： Multicore processing Neural networks Biological system modeling Biological neural networks Computer architecture Large-scale systems Brain modeling Computational modeling Neurons Biology computing Graphics processing unit

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A High-Performance Multi-user Service System for Financial Analytics Based on Web Service and GPU Computation

A High-Performance Multi-user Service System for Financial A...

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international symposium on parallel and distributed processing with applications, ISPA

作者： Gow-Hsing King Zong-You Cai Yan-Ying Lu Jan-Jan Wu Hung-Pin Shih Chao-Rui Chang Dept. Information Management Van-Nung University Tao-Yuan Taiwan Institute of Information Science Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan

In finance, securities, such as stocks, funds, warrants and bonds, are actively traded in financial markets. Abundance of market data and accurate pricing of a security can help the practitioners arbitrage or hedge their position. It can also help researhers and traders design better trading strategies. In this work, we develop a pricing and data/information service system for financial analytics with the following goals: (1) supporting fast pricing and data/information services for massive multiple users, (2) saving cost in hardware equipments and reducing energy consumption, and (3) easy maintenance and service expansion of the system. To achieve the first two goals, we use one traditional server paired with one Tesla C1060 and a set of PCs each paired with an Nvidia x275, and enhance GPU performance using a set of simple yet very effective optimization techniques. For the third goal, we develop our service system based on Web Service and the Service-Oriented-Architecture design principles. Our initial experiment results show that our GPU-based service system can deliver 4.8 tera flops computing speed, which achieves over 6000% performance increase compared to a cluster of eight Intel i7 quad-core servers. Cost-wise, the GPU-based service system costs 40% of the i7 server cluster, and consumes 50% of energy that is required by the i7 cluster. We also gives an overview of our system architecture and describe the workflow for processing pricing and information service requests.

关键词： Pricing Instruction sets Security Graphics processing unit Web services Servers Optimization

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A shared reconfigurable VLIW multiprocessor system

A shared reconfigurable VLIW multiprocessor system

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Fakhar Anjam Stephan Wong Faisal Nadeem Computer Engineering Laboratory Delft University of Technnology Delft Netherlands

ISBN: (纸本)9781424465330

In this paper, we present the design and implementation of an open-source reconfigurable very long instruction word (VLIW) multiprocessor system. This processor is implemented as a softcore on a field-programmable gate arrays (FPGA) and its instruction set architecture (ISA) is based on the Lx/ST200 ISA. This multiprocessor design is based on our earlier ¿-VEX processor design. Since the ¿-VEX processor is a parameterized processor, our multiprocessor design is also parameterized. By utilizing a freely available compiler and simulator in our development framework, we are able to optimize our design and map any application written in C to our multiprocessor system. This VLIW multiprocessor can exploit data level as well as instruction level parallelism inherent in an application and make its execution faster. More importantly, we achieve our results by saving expensive FPGA area through the sharing of resources. The results show that we can achieve two times better performance for our dual-processor system (with shared resources) compared to a uni-processor system or a 2-cluster processor system for applications having data level and instruction level parallelism.

关键词： VLIW Multiprocessing systems parallel processing Field programmable gate arrays Application software Reduced instruction set computing Registers Computer architecture Computer aided instruction Systolic arrays

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Optimization of applications with non-blocking neighborhood collectives via multisends on the Blue Gene/P supercomputer

Optimization of applications with non-blocking neighborhood ...

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international symposium on parallel and distributed processing (IPDPS)

作者： Sameer Kumar Philip Heidelberger Dong Chen Michael Hines IBM Thomas J. Watson Research Center Yorktown Heights NY USA Department of Computer Science Yale University New Heaven CT USA

ISBN: (纸本)9781424464425

We explore the multisend interface as a data mover interface to optimize applications with neighborhood collective communication operations. One of the limitations of the current MPI 2.1 standard is that the vector collective calls require counts and displacements (zero and non-zero bytes) to be specified for all the processors in the communicator. Further, all the collective calls in MPI 2.1 are blocking and do not permit overlap of communication with computation in the same thread of execution. However, multisends are non-blocking calls that permit overlap of computation and communication. We present the record replay persistent optimization to the multisend interface th at minimizes the processor overhead of initiating the collective. We present four different case studies with the multisend API on Blue Gene/P (i) 3D-FFT, (ii) 4D nearest neighbor exchange as used in Quantum Chromodynamics, (iii) NAMD and (iv) neural network simulator NEURON. Performance results show 1.9× speedup with 32 3 3D-FFTs, 1.9× speedup for 4D nearest neighbor exchange with the 2 4 problem, 1.6× speedup in NAMD and almost 3× speedup in NEURON with 256K cells and 1k connections/cell.

关键词： Supercomputers Neurons Neural networks Application software Communication standards Nearest neighbor searches Libraries Proposals Buffer storage Computer science

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J2EE instrumentation for software aging root cause application component determination with AspectJ

J2EE instrumentation for software aging root cause applicati...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Javier Alonso Jordi Torres Josep Ll. Berral Ricard Gavaldà Barcelona Supercomputing Center Department of Computer Architecture Technical University of Catalonia Barcelona Spain Department of Software Department of Computer Architecture Technical University of Catalonia Barcelona Spain Department of Software Technical University of Catalonia Barcelona Spain

ISBN: (纸本)9781424465330

Unplanned system outages have a negative impact on company revenues and image. While the last decades have seen a lot of efforts from industry and academia to avoid them, they still happen and their impact is increasing. According to many studies, one of the most important causes of these outages is software aging. Software aging phenomena refers to the accumulation of errors, usually provoking resource contention, during long running application executions, like web applications, which normally cause applications/systems hang or crash. Determining the software aging root cause failure, not the resource or resources involved in, is a huge task due to the growing day by day complexity of the systems. In this paper we present a monitoring framework based on Aspect Programming to monitor the resources used by every application component in runtime. Knowing the resources used by every component of the application we can determine which components are related to the software aging. Furthermore, we present a case study where we evaluate our approach to determine in a web application scenario, which components are involved in the software aging with promising results.

关键词： Instruments Aging Application software Condition monitoring Computer crashes Computer architecture Degradation Programming profession Runtime Environmental management

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Intra-application cache partitioning

Intra-application cache partitioning

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international symposium on parallel and distributed processing (IPDPS)

作者： Sai Prashanth Muralidhara Mahmut Kandemir Padma Raghavan Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

ISBN: (纸本)9781424464425

Efficient management of shared on-chip resources such as the shared level 2 (L2) cache has become an important problem with the emergence of chip multiprocessors (CMPs). Partitioning the shared cache in chip multiprocessors (CMPs) among concurrently executing applications can provide important benefits such as throughput improvement, fairness guarantees, and quality of service (QoS) enhancements. In this paper, we pose an interesting related question, which is, if partitioning the shared cache space among concurrently executing threads of the same application can enhance the application performance. We address this problem by identifying and speeding up the slowest thread, also termed as the critical path thread, during each execution interval since the overall performance of a multithreaded application is determined by the critical path thread. To do so, we propose a dynamic, runtime system based, cache partitioning scheme that partitions the shared cache space dynamically among the individual threads of a given application. In a nutshell, we wish to take some cache space away from the faster threads and give it to the critical path thread at each execution interval. We show that speeding up the critical path thread this way, results in overall performance enhancement of the application execution in the long term. Our experimental evaluation indicates that, the proposed dynamic cache partitioning scheme yields benefits up to 15% over a shared cache with no partitions, up to 23% over a statically partitioned cache (private cache) and up to 20% over a throughput-oriented scheme.

关键词： Throughput Resource management Quality of service Computer science Performance gain Multicore processing Disaster management

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AuctionNet: Market oriented task scheduling in heterogeneous distributed environments

AuctionNet: Market oriented task scheduling in heterogeneous...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Han Zhao Xiaolin Li Department of Computer Science Scalable Software Systems Laboratory Oklahoma State University Stillwater OK USA

ISBN: (纸本)9781424465330

We propose a suite of market-oriented task scheduling algorithms to build an AuctionNet for heterogeneous distributed environments. In heterogeneous distributed environments, computing nodes are autonomous and owned by different organizations, for example peer-to-peer systems, desktop grids/clouds. To address such diverse heterogeneity and dynamism in systems, applications, and local policies, efficient and fair task scheduling becomes a challenging issue. To cope with such complexity in a distributed and noncooperative environment, we propose to use market-oriented incentive mechanisms to regulate task scheduling in a distributed manner. Further, to accommodate multiple objectives and criteria, we adopt a combined approach leveraging the advantage of both hypergraph theory and incentive mechanisms. We first formulate a general framework of market-oriented task scheduling in distributed systems. We then present two algorithms for task-bundle scheduling. Preliminary results demonstrate the satisfactory performance of our proposed algorithms. The remaining work to complete the PhD dissertation is then presented. The proposed research carries significant intellectual merits and potential broader impacts in the following aspects. (1) We propose the notion of task-bundle for the first time in the literature. Product-bundle has been a common marketing strategy in our daily life for a long time. In the emerging commercial clouds and desktop clouds, task-bundle could be a useful concept for computing and storage markets. (2) We propose efficient distributed mechanisms that are very suitable for such distributed systems. A novel algorithm combining hypergraph and incentive mechanisms achieves multi-objective optimization. (3) We conduct rigorous analytical study and prove that our algorithms ensure efficiency and fairness and in the meantime maximize social welfare. (4) Overall, this proposal lays a solid foundation and sheds light on future research and realworld applicatio

关键词： Processor scheduling distributed computing Job shop scheduling Scheduling algorithm Cloud computing Environmental economics Peer to peer computing Proposals Resource management Grid computing

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A reconfigurable architecture for multicore systems

A reconfigurable architecture for multicore systems

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Annie Avakian Jon Nafziger Amayika Panda Ranga Vemuri Department of Electrical and Computer Engineering University of Cincinnati Cincinnati OH USA

ISBN: (纸本)9781424465330

Various studies concluded that bus-based multiprocessor architectures outperform Network-on-Chip (NoC) architectures when the number of processors is relatively small. On the other hand, NoC architectures offer distinct performance advantages when the number of processors is large. This led to recent proposals for hybrid architectures where each node in a mesh-style packet-switched NoC architecture contains a bus-based subsystem with a small number of processors. Experimental results using select benchmarks demonstrated that these hybrid architectures offer superior performance when compared with purely bus based or purely NoC style architectures. Our studies indicate that while a hybrid architecture is preferable, the optimal number of processors on each bus subsystem varies based on the application. This number appears to vary between 1 and 8 depending on the communication requirements of the application. Further, various applications simultaneously executing on the same system require differing numbers of processors on each bus-based subsystem to minimize the overall throughput time. In this paper, we present a new reconfigurable NoC architecture which allows scalable bus-based multiprocessor subsystems on each node in the NoC. Following configuration, the system provides a multi-bus execution environment where each processor is connected to a bus and the bus-based subsystems communicate via routers connected in a mesh-style configuration. The system can be reconfigured to vary the number of bus subsystems and the number of processors on each subsystem. Each processor contains a Level 1 (L1) cache and each bus, connected to a router, has access to a Level 2 (L2) cache. The L2 caches distributed across the network together form a large virtual L2 that can shared by all the processors in the system via the router network. We present the architecture in detail, discuss a configuration algorithm, and discuss experimental results (using the NS2 and SIMICS simulators)

关键词： Reconfigurable architectures Multicore processing Network-on-a-chip Computer architecture Delay Proposals Computer networks Hardware Routing Throughput

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