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检索条件"任意字段=2nd International Symposium on Parallel and Distributed Processing and Applications"

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Massive Natural Language processing in distributed Environment 20th

Massive Natural Language Processing in Distributed Environm...

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20th international symposium on distributed Computing and Artificial Intelligence, DCAI 2023

作者： Krechowicz, Adam Faculty of Electrical Engineering Automatic Control and Computer Science Kielce University of Technology Kielce Poland

ISBN: (纸本)9783031383175

Natural Language processing (NLP) models are one of the most promising topics nowadays. applications like ChatGPT uncover the power of such models and their broad applications. However, developing such models requires an extensive amount of training data sets to operate on. As such data sets grow, it becomes impossible to process them on a single machine, even using parallel computations. In this paper, the problem of distributing the NLP computations is taken into consideration. The Scalable distributed Two-Layer Data Structures were used to organize the distributed environment. Stanford Core NLP library was used to perform accurate NLP computations. The experiments focused on the efficiency of the computation in the distributed environment and the accuracy of the predictions in relation to the scale of the distributions. The results clearly show that an increase in performance can be obtained without a significant decrease in accuracy. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Natural language processing systems

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O(N) distributed direct factorization of structured dense matrices using runtime systems 23

O(N) distributed direct factorization of structured dense ma...

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52nd international Conference on parallel processing (ICPP)

作者： Deshmukh, Sameer Ma, Qinxiang Yokota, Rio Bosilca, George Tokyo Inst Technol Sch Comp Tokyo Japan Tokyo Inst Technol Global Sci Informat & Comp Ctr Tokyo Japan Univ Tennessee Innovat Comp Lab Knoxville TN USA

ISBN: (纸本)9798400708435

Structured dense matrices result from boundary integral problems in electrostatics and geostatistics, and also Schur complements in sparse preconditioners such as multi-frontal methods. Exploiting the structure of such matrices can reduce the time for dense direct factorization from O(N-3) to O(N). The Hierarchically Semi-Separable (HSS) matrix is one such low rank matrix format that can be factorized using a Cholesky-like algorithm called ULV factorization. The HSS-ULV algorithm is highly parallel because it removes the dependency on trailing sub-matrices at each HSS level. However, a key merge step that links two successive HSS levels remains a challenge for efficient parallelization. In this paper, we use an asynchronous runtime system PaRSEC with the HSS-ULV algorithm. We compare our work with STRUMPACK and LORAPO, both state-of-the-art implementations of dense direct low rank factorization, and achieve up to 2x better factorization time for matrices arising from a diverse set of applications on up to 128 nodes of Fugaku for similar or better accuracy for all the problems that we survey.

关键词： low rank approximation runtime systems HSS matrix distributed

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ActIPP: Active Intellectual Property Protection of Edge-Level Graph Learning for distributed Vehicular Networks 22

ActIPP: Active Intellectual Property Protection of Edge-Leve...

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22nd IEEE international symposium on parallel and distributed processing with applications, ISPA 2024

作者： Yang, Xiao Li, Gaolei Dong, Mianxiong Ota, Kaoru Zhang, Chaofeng Peng, Xiting Li, Jianhua Shanghai Jiao Tong University China Muroran Institute of Technology Japan Advanced Institute of Industrial Technology China Shenyang University of Technology China

ISBN: (纸本)9798331509712

Edge-Level Graph Learning System (EGLS) exhibits diverse applicability in management of distributed vehicular networks, e.g., flow prediction, route planning, and accident forecasting. For the EGLS training, expensive hardware resource consumption, traffic data collection, and dedicated training procedures make the learning algorithms become valuable intellectual property (IP) for the EGLS owner (e.g., Uber and Lyft), and they cannot tolerate the infringement act of their models' intellectual property. To enhance its IP protection, we present ActIPP, the first active IP protection methodology for EGLS, which incorporates a built-in access control function in the model to safeguard against unauthorized queries. Specifically, it is achieved via a creative edge backdoor mechanism, wherein the edge training samples are poisoned via user-specific access tokens to induce legal outputs from a well-trained EGLS model for authorized users. Moreover, related token regulating strategies were proposed to dynamically realize the addition and revocation of user tokens by model retraining to guarantee access control in EGLS. Additionally, a Graph Mutual Information-based adaptive token generation method is presented to augment the access control embedding. Based on experiments with various real-world datasets, ActIPP demonstrates high success rates of IP protection (accuracy drop © 2024 IEEE.

关键词： Access control models

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Communication-Avoiding Optimizations for Large-Scale Unstructured-Mesh applications with OP2 23

Communication-Avoiding Optimizations for Large-Scale Unstruc...

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52nd international Conference on parallel processing (ICPP)

作者： Ekanayake, Suneth D. Reguly, Istvan Z. Luporini, Fabio Mudalige, Gihan R. Univ Warwick Coventry W Midlands England Pazmany Peter Catholic Univ Budapest Hungary Devito Codes London England

ISBN: (纸本)9798400708435

In this paper, we investigate data movement-reducing and communication-avoiding optimizations and their practicable implementation for large-scale unstructured-mesh applications. Utilizing the high-level abstraction of the OP2 DSL for the unstructured-mesh class of codes, we reason about techniques for reduced communications across a consecutive sequence of loops - a loop-chain. The careful trade-off with increased redundant computation in place of data movement is analyzed for distributed-memory parallelization. A new communication-avoiding (CA) back-end for OP2 is designed, codifying these techniques such that they can be applied automatically to any OP2 application. The back-end is extended to operate on a cluster of GPUs, integrating GPU-to-GPU communication with CUDA, in combination with MPI. The new CA back-end is applied automatically to two non-trivial applications, including the OP2 version of Rolls-Royce's production CFD application, Hydra. Performance is investigated on both CPU and GPU clusters on representative problems of 8M and 24M node mesh sizes. Results demonstrate how for select configurations the new CA back-end provides between 30 - 65% runtime reductions for the loop-chains in these applications for the mesh sizes on both an HPE Cray EX system and an NVIDIA V100 GPU cluster. We model and examine the determinants and characteristics of a given unstructured-mesh loopchain that can lead to performance benefits with CA techniques, providing insights into the general feasibility and profitability of using the optimizations for this class of applications.

关键词： Communication-avoiding algorithms OP2 Unstructured-mesh

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FRAME 2022: The 2nd Workshop on Flexible Resource and Application Management on the Edge 22

FRAME 2022: The 2nd Workshop on Flexible Resource and Applic...

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31st international symposium on High-Performance parallel and distributed Computing (HPDC)

作者： Ferrucci, Luca Coppola, Massimo Kavalionak, Hanna Kontopoulos, Ioannis ISTI Consiglio Nazl Ric Pisa Italy Harokopio Univ Athens Athens Greece

ISBN: (纸本)9781450391993

The 2nd internationalWorkshop on Flexible Resource and Application Management on the Edge (FRAME 2022) is dedicated to the so-called Cloud/Edge Continuum, where Cloud and Edge infrastructures can work together to fulfill requirements from a variety of NextGen applications. Clouds provide appropriate levels of performance to large groups of different users, whereas Edge resources act as a first layer of computing capacity that is closer to the user, to reduce the service latency. With respect to Clouds, Edge infrastructures typically are composed of heterogeneous and constrained resources and introduce new challenges from the viewpoint of security, orchestration and resource management. Tackling these new issues calls for innovative combinations of tools and abstractions, where AI and machine learning techniques complement algorithmic orchestration and optimization, bringing about new levels of distributed adaptivity and self-management. As real-time data-driven decisions can be promptly taken on the spot, without the need to wait for data to travel to the Cloud and back, also interactive and time-sensitive services like the immersive data processing of Extended Reality (XR) applications can be partially extended toward the edge, thus exploiting a better computation to communication tradeoff and smoother connections to improve their QoE and remote collaboration. The FRAME'22 workshop proceedings are available at: https://***/***?id=3526059.

关键词： network mobility edge storage autonomic management federated learning cloud computing resource management artificial intelligence edge continuum virtualization 3d point cloud cloud federation edge computing machine learning edge orchestration

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On Task Assignment and Scheduling for distributed Job Execution 22

On Task Assignment and Scheduling for Distributed Job Execut...

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22nd IEEE/ACM international symposium on Cluster, Cloud and Internet Computing (CCGrid)

作者： Guan, Yitong Tang, Xueyan Nanyang Technol Univ Sch Comp Sci & Engn Singapore 639798 Singapore

ISBN: (纸本)9781665499569

It is common for big data applications to run across multiple datacenters or machine clusters because the data inputs are distributed over different locations. This paper studies a job scheduling problem for distributed job execution in which the data inputs to jobs may be replicated across multiple locations so that each task of a job can be executed at any one of these locations. To schedule the jobs, we need to determine the processing locations for the tasks of each job and the execution order of the tasks at each location. We focus on the objective of minimizing the average job response time. We first design a task assignment algorithm to balance the task allocation among various locations. We then further develop integrated solutions that conduct task assignment and scheduling together. We experimentally evaluate our algorithms using real job traces. The results show that our algorithms can significantly reduce the job response times compared to a baseline that allocates each task to a fixed location for processing.

关键词： Schedules Cloud computing Processor scheduling distributed databases Big Data applications Time factors Resource management

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Communication-Efficient Cluster Scalable Genomics Data processing Using Apache Arrow Flight 21

Communication-Efficient Cluster Scalable Genomics Data Proce...

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21st IEEE international symposium on parallel and distributed Computing (ISPDC)

作者： Ahmad, Tanveer Ma, Chengxin Al-Ars, Zaid Hofstee, H. Peter Delft Univ Technol Delft Netherlands

ISBN: (数字)9781665488020

ISBN: (纸本)9781665488020

Current cluster scaled genomics data processing solutions rely on big data frameworks like Apache Spark, Hadoop and HDFS for data scheduling, processing and storage. These frameworks come with additional computation and memory overheads by default. It has been observed that scaling genomics dataset processing beyond 32 nodes is not efficient on such frameworks. To overcome the inefficiencies of big data frameworks for processing genomics data on clusters, we introduce a low-overhead and highly scalable solution on a SLURM based HPC batch system. This solution uses Apache Arrow as in-memory columnar data format to store genomics data efficiently and Arrow Flight as a network protocol to move and schedule this data across the HPC nodes with low communication overhead. As a use case, we use NGS short reads DNA sequencing data for pre-processing and variant calling applications. This solution outperforms existing Apache Spark based big data solutions in term of both computation time (2x) and lower communication overhead (more than 20-60% depending on cluster size). Our solution has similar performance to MPI-based HPC solutions, with the added advantage of easy programmability and transparent big data scalability. The whole solution is Python and shell script based, which makes it flexible to update and integrate alternative variant callers. Our solution is publicly available on GitHub at https://***/abs-tudelft/time-to-flyhigh/tree/main/genomics

关键词： Genomics Whole Genome/Exome Sequencing Big Data Apache Arrow In-Memory Plasma Object Store parallel processing

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GPU-Enabled Asynchronous Multi-level Checkpoint Caching and Prefetching 23

GPU-Enabled Asynchronous Multi-level Checkpoint Caching and ...

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32nd international symposium on High-Performance parallel and distributed Computing (HPDC) part of the ACM Federated Computing Research Conference (FCRC)

作者： Maurya, Avinash Rafique, M. Mustafa Tonellot, Thierry AlSalem, Hussain J. Cappello, Franck Nicolae, Bogdan Rochester Inst Technol Rochester NY 14623 USA Saudi Aramco Explorat & Petr Engn Adv Res Ctr Dhahran Saudi Arabia Argonne Natl Lab Lemont IL USA

ISBN: (纸本)9798400701559

Checkpointing is an I/O intensive operation increasingly used by High-Performance Computing (HPC) applications to revisit previous intermediate datasets at scale. Unlike the case of resilience, where only the last checkpoint is needed for application restart and rarely accessed to recover from failures, in this scenario, it is important to optimize frequent reads and writes of an entire history of checkpoints. State-of-the-art checkpointing approaches often rely on asynchronous multi-level techniques to hide I/O overheads by writing to fast local tiers (e.g. an SSD) and asynchronously flushing to slower, potentially remote tiers (e.g. a parallel file system) in the background, while the application keeps running. However, such approaches have two limitations. First, despite the fact that HPC infrastructures routinely rely on accelerators (e.g. GPUs), and therefore a majority of the checkpoints involve GPU memory, efficient asynchronous data movement between the GPU memory and host memory is lagging behind. Second, revisiting previous data often involves predictable access patterns, which are not exploited to accelerate read operations. In this paper, we address these limitations by proposing a scalable and asynchronous multi-level checkpointing approach optimized for both reading and writing of an arbitrarily long history of checkpoints. Our approach exploits GPU memory as a first-class citizen in the multi-level storage hierarchy to enable informed caching and prefetching of checkpoints by leveraging foreknowledge about the access order passed by the application as hints. Our evaluation using a variety of scenarios under I/O concurrency shows up to 74x faster checkpoint and restore throughput as compared to the state-of-art runtime and optimized unified virtual memory (UVM) based prefetching strategies and at least 2x shorter I/O wait time for the application across various workloads and configurations.

关键词： High-Performance Computing (HPC) Graphics processing Unit (GPU) asynchronous multi-level checkpointing hierarchical cache management prefetching

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Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinger Quantum Circuit Simulations

Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinge...

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2023 IEEE international parallel and distributed processing symposium Workshops, IPDPSW 2023

作者： Podobas, Artur KTH Royal Institute of Technology School of Electrical Engineering and Computer Science Stockholm Sweden

ISBN: (纸本)9798350311990

Quantum computing is emerging as an important (but radical) technology that might take us beyond Moore's law for certain applications. Today, in parallel with improving quantum computers, computer scientists are relying heavily on quantum circuit simulators to develop algorithms. Most existing quantum circuit simulators run on general-purpose CPUs or GPUs. However, at the same time, quantum circuits themselves offer multiple opportunities for parallelization, some of which could map better to other architecture- architectures such as reconfigurable systems. In this early work, we created a quantum circuit simulator system called Q2Logic. Q2Logic is a coarse-grained reconfigurable architecture (CGRA) implemented as an overlay on Field-Programmable Gate Arrays (FPGAs), but specialized towards quantum simulations. We described how Q2Logic has been created and reveal implementation details, limitations, and opportunities. We end the study by empirically comparing the performance of Q2Logic (running on a Intel Agilex FPGA) against the state-of-the-art framework SVSim (running on a modern processor), showing improvements in three large circuits(#qbit≥27), where Q2Logic can be up-to 7x faster. © 2023 IEEE.

关键词： Circuit simulation

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QuaL²M : Learning Quantitative Performance of Latency-Sensitive Code 36

QuaL<SUP>2</SUP>M : Learning Quantitative Performance of Lat...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Sathanur, Arun Tallent, Nathan R. Konsor, Patrick Koyanagi, Ken McLaughlin, Ryan Olivas, Joseph Chynoweth, Michael Pacific Northwest Natl Lab Seattle WA 98109 USA Pacific Northwest Natl Lab Richland WA 99352 USA Intel Hillsboro OR USA Intel Folsom CA USA Intel Albuquerque NM USA

ISBN: (纸本)9781665497473

Quantitative performance predictions are more informative than qualitative. However, modeling of latency-sensitive code, with cost distributions of high variability and heavy tails, is extremely difficult. To date, quantitative prediction for such code has been limited to either special cases (e.g., best-case performance) or resource-intensive methods (e.g., simulation). We present QuaL(2)M, a method for learning quantitative performance of latency-sensitive CPU code. We collect high resolution data (superblock, i.e., short instruction sequence), with challenging cost distributions, from several applications over a range of inputs and times. For each superblock, QuaL(2)M predicts both expected and degraded performance in cycles. QuaL(2)M distinguishes superblock behavior by combining lightweight telemetry from performance monitoring units and readily obtainable compiler execution models. Compared to two state-of-the art methods, on our largest dataset, QuaL(2)M achieves an R-2 of 0.87 vs. 0.37 and 0.39. The trained models can be used for online performance diagnosis and adaptation.

关键词： performance prediction superblocks ensemble decision trees deep learning QuaLM

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