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30th international conference on VLSI Design / 16th international conference on Embedded Systems (VLSID)

作者： Mandal, Sudipa Da Costa, Antonio Bruto Hazra, Aritra Dasgupta, Pallab Naware, Bhushan Chunduri, Rama Mohan Basu, Sanjib Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India Indian Inst Technol Madras Tamil Nadu India Intel Technol India Pvt Ltd Bangalore Karnataka India

ISBN: (纸本)9781509057405

System on Chip (SoC) designs today have a large number of power domains regulated by complex on-chip power management logic. the power management logic is primarily digital in nature, but it relies on analog components such as Low Dropout Regulators (LDO) and Phase-Locked Loops (PLL) for delivery of regulated voltages and clock frequencies. In low power designs, such analog components may also be powered down at times, and hence power domains are defined around modules containing these components. the digital brain of the power management logic must correctly consider the latencies of the analog components in the power management fabric while switching the power domains driven by these components. this is a task which has become extremely complex by virtue of the multitude of LDOs and PLLs in a modern integrated circuit, and the numerous domains that they drive. this paper presents, for the first time, a formal verification methodology for automatically generating the necessary assertions from an extended syntax of the Unified Power Format (UPF) and proving them on the power management logic using available industrial formal verification tools.

关键词： Phase locked loops Clocks Timing Fabrics Computer bugs Sequential analysis Voltage control

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Online Learning of logic Based Neural Network Structures 1

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30th international conference on Inductive logic programming (ILP) held as part of the 1st international Joint conference on Learning and Reasoning (IJCLR)

作者： Guimaraes, Victor Costa, Vitor Santos Univ Porto CRACS Porto Portugal Univ Porto DCC FCUP Porto Portugal

ISBN: (数字)9783030974541

ISBN: (纸本)9783030974541;9783030974534

In this paper, we present two online structure learning algorithms for NeuralLog, NeuralLog+OSLR and NeuralLog+OMIL. NeuralLog is a system that compiles first-order logic programs into neural networks. Both learning algorithms are based on Online Structure Learner by Revision (OSLR). NeuralLog+OSLR is a port of OSLR to use NeuralLog as inference engine;while NeuralLog+OMIL uses the underlying mechanism from OSLR, but with a revision operator based on Meta-Interpretive Learning. We compared both systems with OSLR and RDN-Boost on link prediction in three different datasets: Cora, UMLS and UWCSE. Our experiments showed that NeuralLog+OMIL outperforms both the compared systems on three of the four target relations from the Cora dataset and in the UMLS dataset, while both NeuralLog+OSLR and NeuralLog+OMIL outperform OSLR and RDNBoost on the UWCSE, assuming a good initial theory is provided.

关键词： Online Learning Inductive logic programming Meta-Interpretive Learning Neural Network Neural-Symbolic Learning and Reasoning theory Revision from Examples

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Ultra-compact and Fast All-optical Photonic Crystal Half-subtractor logic Gate 30

Ultra-compact and Fast All-optical Photonic Crystal Half-sub...

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30th international conference on Electrical Engineering, ICEE 2022

作者： Veisi, Ehsan Seifouri, Mahmood Olyaee, Saeed Shahid Rajaee Teacher Training University Faculty of Electrical Engineering Tehran Iran Tehran Iran

ISBN: (纸本)9781665480871

Despite developments in all-optical devices, there is a tremendous demand for various innovative all-optical structures containing dual capabilities to attain all-optical processors. this paper proposes an ultra-compact and ultra-fast structure for an all-optical half-subtractor logic gate. An all-optical photonic crystal half-subtractor is applicable in all-optical logic processors. In this study, the plane wave expansion method was used to design the structure. Also, the finite-difference time-domain method was used to analyze the proposed structure numerically. the footprint structure was about 42 mu {m}^logic and the maximum time delay was about 60 fs. the contrast ratio for the proposed all-optical half-subtractor structure was 18.4 dB for Port D and 6.3 dB for Port B. the findings indicated that the proposed ultra-compact structure reduced the time delay at the proposed logic gate. It can be concluded that the proposed structure ensures no performance decline. © 2022 IEEE.

关键词： logic gates

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LPMLNModels: A Parallel Solver for LP^MLN 30

LPMLNModels: A Parallel Solver for LP<SUP>MLN</SUP>

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30th IEEE international conference on Tools with Artificial Intelligence (ICTAI)

作者： Wu, Wei Xu, Hongxiang Zhang, Shutao Duan, Jiaqi Wang, Bin Zhang, Zhizheng He, Chenglong Zong, Shiqiang Southeast Univ Sch Comp Sci & Engn Nanjing Jiangsu Peoples R China China Elect Technol Grp Corp Res Inst 28 Sci & Technol Informat Syst Engn Lab Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781538674499

LPMLN extends the language of Answer Set programming (ASP) by assigning a weight degree to each rule so that its stable models do not have to satisfy all LPMLN rules, which is rooted in the manner of Markov logic Networks (MLN) to handle the uncertainties and inconsistencies in knowledge representation and reasoning. Due to its expressibility, LPMLN has been employed in several real world applications. However, an LPMLN program is much harder to solve than its unweighted counterpart (an ASP program), and only some preliminary solvers have been implemented so far, which is preventing further studies in both theoretical and practical sides. there are three main contributions in this paper. Firstly, we present an LPMLN solver: LPMLNModels, which is able to run concurrently. Secondly, we present parallel methods in LPMLNModels. For splitting set method, we present an algorithm to generate a proper splitting set, which is an essential part of the method. For augmented subset method, we present a heuristic method to improve its performance. Finally, we present hybrid methods in LPMLNModels to better utilize the parallel methods. the experimental results show that our algorithms and improvements in this paper works and hybrid methods have better performance in general.

关键词： Lp(MLN) programming inference engine parallel solver

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Question recommender with ML Business logic

Question recommender with ML Business Logic

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30th international conference on Information Technology Interfaces

作者： Burdescu, Dumitru Dan Mihaescu, Marian Cristian Logofatu, Bogdan Univ Craiova Fac Automat Comp & Elect Software Engn Dept Bvd Decebal 107 Craiova 200440 Dolj Romania Univ Bucharest Sect 5 CREDIS Dept Bucharest Romania

ISBN: (纸本)9789537138127

Advising the learner regarding the resources he needs to access in order to obtain best learning proficiency is one of the main issues in Learning Management Systems. this paper presents an original method of recomending questions that need to be taken into consideration for answering by learner. the Business logic that decides what questions are displayed to student is based on Machine Learning algorithms, more exactly on Naive Bayes classifier.

关键词： Bayes procedures educational technology

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A Stochastic Reconfigurable Architecture for Fault-Tolerant Computation with Sequential logic

A Stochastic Reconfigurable Architecture for Fault-Tolerant ...

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30th IEEE international conference on Computer Design (ICCD)

作者： Li, Peng Qian, Weikang Lilja, David J. Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55414 USA

ISBN: (纸本)9781467330527

Computation performed on stochastic bit streams is less efficient than that based on a binary radix because of its long latency. However, for certain complex arithmetic operations, computation on stochastic bit streams can consume less energy and tolerate more soft errors. In addition, the latency issue could be solved by using a faster clock frequency or in combination with a parallel processing approach. To take advantage of this computing technique, previous work proposed a combinational logic-based reconfigurable architecture to perform complex arithmetic operations on stochastic streams of bits. In this paper, we enhance and extend this reconfigurable architecture using sequential logic. Compared to the previous approach, the proposed reconfigurable architecture takes less hardware area and consumes less energy, while achieving the same performance in terms of processing time and fault-tolerance.

关键词： Reconfigurable architectures

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Review of Open-source Microcontroller and Programmable logic Development Boards 30

Review of Open-source Microcontroller and Programmable Logic...

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30th international Scientific conference Electronics, ET 2021

作者： Rankovska, Valentina V. Technical University of Gabrovo Faculty of Electrical and Electronic Engineering Department of Electronics Gabrovo5300 Bulgaria

ISBN: (纸本)9781665445184

the paper provides a brief review of open source development hardware, based on microcontrollers and programmable logic integrated circuits with Field-Programmable Gate Arrays (FPGA) architecture. their main features and advantages are examined. they include all the required components for the microcontroller or programmable logic to operate, and are usually small sized, cheap and flexible, thus allowing to be implemented in teaching and home students' projects. © 2021 IEEE.

关键词： Microcontrollers

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Terminating Non-disjoint Combined Unification 30th

Terminating Non-disjoint Combined Unification

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30th international conference on logic-Based Program Synthesis and Transformation (LOPSTR)

作者： Erbatur, Serdar Marshall, Andrew M. Ringeissen, Christophe Univ Texas Dallas Richardson TX 75083 USA Univ Mary Washington Fredericksburg VA USA Univ Lorraine LORIA INRIA CNRS F-54000 Nancy France

ISBN: (纸本)9783030684457;9783030684464

the equational unification problem, where the underlying equational theory may be given as the union of component equational theories, appears often in practice in many fields such as automated reasoning, logic programming, declarative programming, and the formal analysis of security protocols. In this paper, we investigate the unification problem in the non-disjoint union of equational theories via the combination of hierarchical unification procedures. In this context, a unification algorithm known for a base theory is extended with some additional inference rules to take into account the rest of the theory. We present a simple form of hierarchical unification procedure. the approach is particularly well-suited for any theory where a unification procedure can be obtained in a syntactic way using transformation rules to process the axioms of the theory. Hierarchical unification procedures are exemplified with various theories used in protocol analysis. Next, we look at modularity methods for combining theories already using a hierarchical approach. In addition, we consider a new complexity measure that allows us to obtain terminating (combined) hierarchical unification procedures.

关键词： logic programming

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claspfolio 2: Advances in Algorithm Selection for Answer Set programming

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thEORY AND PRACTICE OF logic programming 2014年第4-5期14卷 569-585页

作者： Hoos, Holger Lindauer, Marius Schaub, Torsten Univ British Columbia Vancouver BC V5Z 1M9 Canada Univ Freiburg Freiburg Germany Univ Potsdam Potsdam Germany

Building on the award-winning, portfolio-based ASP solver claspfolio, we present claspfolio 2, a modular and open solver architecture that integrates several different portfolio-based algorithm selection approaches and techniques. the claspfolio 2 solver framework supports various feature generators, solver selection approaches, solver portfolios, as well as solver-schedule-based pre-solving techniques. the default configuration of claspfolio 2 relies on a light-weight version of the ASP solver clasp to generate static and dynamic instance features. the flexible open design of claspfolio 2 is a distinguishing factor even beyond ASP. As such, it provides a unique framework for comparing and combining existing portfolio-based algorithm selection approaches and techniques in a single, unified framework. Taking advantage of this, we conducted an extensive experimental study to assess the impact of different feature sets, selection approaches and base solver portfolios. In addition to gaining substantial insights into the utility of the various approaches and techniques, we identified a default configuration of claspfolio 2 that achieves substantial performance gains not only over clasp's default configuration and the earlier version of claspfolio, but also over manually tuned configurations of clasp.

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Investigating Bloom's Cognitive Skills in Foundation and Advanced programming Courses from Students' Discussions 30

Investigating Bloom's Cognitive Skills in Foundation and Adv...

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30th international conference on Computers in Education (ICCE)

作者： Lim, Joel J. W. Gottipati, Swapna Shim, Kyong Jin Singapore Management Univ Sch Comp & Informat Syst Singapore Singapore

ISBN: (纸本)9789869721493

programming courses provide students with the skills to develop complex business applications. Teaching and learning programming is challenging, and collaborative learning is proposed to help with this challenge. Online discussion forums promote networking with other learners such that they can build knowledge collaboratively. It aids students open their horizons of thought processes to acquire cognitive skills. Cognitive analysis of discussion is critical to understand students' learning process. In this paper, we propose Bloom's taxonomy based cognitive model for programming discussion forums. We present machine learning (ML) based solution to extract students' cognitive skills. Our evaluations on compupting courses show that ensemble model performs better with an average F1-score of 76%.

关键词： Discussion forum bloom's taxonomy cognitive skills programming posts machine learning

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