Parallel load counters are a specific category of counters that offer the flexibility of being loaded with any desired sequence. While counters are usually described as basic building blocks in textbooks, current rese...
Parallel load counters are a specific category of counters that offer the flexibility of being loaded with any desired sequence. While counters are usually described as basic building blocks in textbooks, current research efforts are focused on enhancing their efficiency in terms of power consumption, area utilization, and propagation delay. this study introduces three innovative implementations of parallel load counters that are optimized for power, delay, and area based on two well-established textbook approaches. the optimization methods employed in this work utilize logic minimization of the textbook counters and incorporate the use of True Single-Phase Clock-FlipFlops (TSPCFF) instead of conventional registers to further enhance efficiency. Post-layout simulations employing 180nm CMOS technology demonstrate that the proposed counters achieve $\sim 3.4 \times$ lower power consumption, $\sim 2 \times$ higher maximum frequency, $\sim 4.9 \times$ reduced latency and $\sim 2 \times$ smaller area footprint compared to the traditional methods. In addition, the proposed solutions are less susceptible to noise caused by the supply voltage and temperature fluctuations. We believe that this study serves as a valuable reference for circuit designers to further optimize design efficiency and meet specific requirements.
Extensions of Dung's Argumentation Framework (AF) include the class of Recursive Bipolar AFs (Rec-BAFs), i.e. AFs with recursive attacks and supports. We show that a Rec-BAF Delta can be translated into a logic pr...
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ISBN:
(纸本)9780999241196
Extensions of Dung's Argumentation Framework (AF) include the class of Recursive Bipolar AFs (Rec-BAFs), i.e. AFs with recursive attacks and supports. We show that a Rec-BAF Delta can be translated into a logic program P-Delta so that the extensions of Delta under different semantics coincide with subsets of the partial stable models of P-Delta.
Topological semantics for modal logic based on the Cantor derivative operator gives rise to derivative logics, also referred to as d-logics. Unlike logics based on the topological closure operator, d-logics have not p...
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the proceedings contain 14 papers. the topics discussed include: data-aware process networks;integrating a functional pattern-based IR into MLIR;compiling data-parallel datalog;PGZ: automatic zero-value code specializ...
ISBN:
(纸本)9781450383257
the proceedings contain 14 papers. the topics discussed include: data-aware process networks;integrating a functional pattern-based IR into MLIR;compiling data-parallel datalog;PGZ: automatic zero-value code specialization;exploring the space of optimization sequences for code-size reduction: insights and tools;polybench/python: benchmarking python environments with polyhedral optimizations;a modern compiler for the French tax code;communication-safe web programming in TypeScript with routed multiparty session types;helper function inlining in dynamic binary translation;lightning BOLT: powerful, fast, and scalable binary optimization;compact native code generation for dynamic languages on micro-core architectures;and deep NLP-based co-evolvement for synthesizing code analysis from natural language.
Neuromorphic Computing offers energy efficient AI inference for Edge Computing as well as morphologically adaptive and complex machine learning systems inspired by the nature. Hardware-software codesign approach prese...
Neuromorphic Computing offers energy efficient AI inference for Edge Computing as well as morphologically adaptive and complex machine learning systems inspired by the nature. Hardware-software codesign approach presents the optimum solution for performing neuromorphic computations. Hardware Software Codesign is an embedded systems approach that target sharing computational costs between the software and hardware with using system-on-chip (SoC) that contains general purpose microprocessors, FPGAs, ASIC cores, memory block periperals and interconnection buses in one *** this study, we determine the basic requirements of neuromorphic hardware systems and the problems in the hardware design. We use the hardware-software codesign approach to solve those problems. By comparing the HDL models of spiking neurons with a programmable spiking neuron designed with hardware-software codesign approach in terms of speed, timing and hardware cost, we demonstrate the superiority of the hardware-software co-design approach in neuromorphic computing over pure hardware or pure software solutions.
Physical side-channel attacks represent a great challenge for today’s chip design. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, many other effects potentially affect the secur...
Physical side-channel attacks represent a great challenge for today’s chip design. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, many other effects potentially affect the security of CMOS chips analogously by affecting mostly static behaviour of the chip, including aging, ionizing radiation, or non-ionizing illumination of the CMOS. Vulnerabilities exploiting data dependency in CMOS static power were already demonstrated in practice and the analogous vulnerability exploiting light-modulated static power was demonstrated by simulation. this work confirms the CMOS vulnerability related to the light-modulated data-dependent static power experimentally and discusses future work.
By running simulation models on FPGAs, their execution speed can be significantly improved, at the cost of increased development effort. this paper describes a project to develop a tool which converts simulation model...
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ISBN:
(纸本)9781728199023
By running simulation models on FPGAs, their execution speed can be significantly improved, at the cost of increased development effort. this paper describes a project to develop a tool which converts simulation models written in high level languages into fast FPGA hardware. the tool currently converts code written using custom C++ data types into Verilog. A model of a hybrid electric vehicle is used as a case study, and the resulting hardware runs significantly faster than on a general purpose CPU.
the proceedings contain 24 papers. the special focus in this conference is on programming. the topics include: Sound and Complete Concolic Testing for Higher-order Functions;strong-Separation logic;types for Complexit...
ISBN:
(纸本)9783030720186
the proceedings contain 24 papers. the special focus in this conference is on programming. the topics include: Sound and Complete Concolic Testing for Higher-order Functions;strong-Separation logic;types for Complexity of Parallel Computation in Pi-Calculus;checking Robustness Between Weak Transactional Consistency Models;verified Software Units;an Automated Deductive Verification Framework for Circuit-building Quantum Programs;nested Session Types;coupled Relational Symbolic Execution for Differential Privacy;graded Hoare logic and its Categorical Semantics;coupled relational symbolic execution for differential privacy;graded hoare logic and its categorical semantics;etaps foreword;preface;For a Few Dollars More: Verified Fine-Grained Algorithm Analysis Down to LLVM;run-time Complexity Bounds Using Squeezers;complete trace models of state and control;session Coalgebras: A Coalgebraic View on Session Types and Communication Protocols;correctness of Sequential Monte Carlo Inference for Probabilistic programming Languages;densities of Almost Surely Terminating Probabilistic Programs are Differentiable Almost Everywhere;graded Modal Dependent Type theory;automated Termination Analysis of Polynomial Probabilistic Programs;bayesian strategies: probabilistic programs as generalised graphical models;data Flow Analysis of Asynchronous Systems using Infinite Abstract Domains.
We propose a mechanism for automating discovery of definitions, that, when added to a logic system for which we have a theorem prover, extends it to support an embedding of a new logic system into it. As a result, the...
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ISBN:
(纸本)9783030684457;9783030684464
We propose a mechanism for automating discovery of definitions, that, when added to a logic system for which we have a theorem prover, extends it to support an embedding of a new logic system into it. As a result, the synthesized definitions, when added to the prover, implement a prover for the new logic. As an instance of the proposed mechanism, we derive a Prolog theorem prover for an interesting but unconventional epistemic logic by starting from the sequent calculus G4IP that we extend with operator definitions to obtain an embedding in intuitionistic propositional logic (IPC). With help of a candidate definition formula generator, we discover epistemic operators for which axioms and theorems of Artemov and Protopopescu's Intuitionistic Epistemic logic (IEL) hold and formulas expected to be non-theorems fail. We compare the embedding of IEL in IPC with a similarly discovered successful embedding of Dosen's double negation modality, judged inadequate as an epistemic operator. Finally, we discuss the failure of the necessitation rule for an otherwise successful S4 embedding and share our thoughts about the intuitions explaining these differences between epistemic and alethic modalities in the context of the Brouwer-Heyting-Kolmogorov semantics of intuitionistic reasoning and knowledge acquisition.
Qualitative Choice logic (QCL) and Conjunctive Choice logic (CCL) are formalisms for preference handling, with especially QCL being well established in the field of AI. So far, analyses of these logics need to be done...
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ISBN:
(纸本)9780999241196
Qualitative Choice logic (QCL) and Conjunctive Choice logic (CCL) are formalisms for preference handling, with especially QCL being well established in the field of AI. So far, analyses of these logics need to be done on a case-by-case basis, albeit they share several common features. this calls for a more general choice logic framework, with QCL and CCL as well as some of their derivatives being particular instantiations. We provide such a framework, which allows us, on the one hand, to easily define new choice logics and, on the other hand, to examine properties of different choice logics in a uniform setting. In particular, we investigate strong equivalence, a core concept in nonclassical logics for understanding formula simplification, and computational complexity. Our analysis also yields new results for QCL and CCL. For example, we show that the main reasoning task regarding preferred models is theta P-2-complete for QCL and CCL, while being Delta P-2-complete for a newly introduced choice logic.
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