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30th IEEE international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Kung, H. T. McDanel, Bradley Zhang, Sai Qian Dong, Xin Chen, Chih Chiang Harvard Univ Cambridge MA 02138 USA MediaTek Hsinchu Taiwan

ISBN: (纸本)9781728116013

We present the Maestro memory-on-logic 3D-IC architecture for coordinated parallel use of a plurality of systolic arrays (SAs) in performing deep neural network (DNN) inference. Maestro reduces under-utilization common for a single large SA by allowing parallel use of many smaller SAs on DNN weight matrices of varying shapes and sizes. In order to buffer immediate results in memory blocks (MBs) and provide coordinated high-bandwidth communication between SAs and MBs in transferring weights and results Maestro employs three innovations. (1) An SA on the logic die can access its corresponding MB on the memory die in short distance using 3D-IC interconnects, (2) through an efficient switch based on H-trees, an SA can access any MB with low latency, and (3) the switch can combine partial results from SAs in an elementwise fashion before writing back to a destination MB. We describe the Maestro architecture, including a circuit and layout design, detail scheduling of the switch, analyze system performance for real-time inference applications using input with batch size equal to one, and showcase applications for deep learning inference, with ShiftNet for computer vision and recent Transformer models for natural language processing. For the same total number of systolic cells, Maestro, with multiple smaller SAs, leads to 16x and 12x latency improvements over a single large SA on ShiftNet and Transformer, respectively. Compared to a floating-point GPU implementation of ShiftNet and Transform, a baseline Maestro system with 4,096 SAs (each with 8x8 systolic cells) provides significant latency improvements of 30x and 47x, respectively.

关键词： systolic arrays memory-on-logic 3D-IC computer architecture combining switch deep neural network convolutional neural network Transformer

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Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication 30

Using Residue Number Systems to Accelerate Deterministic Bit...

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30th IEEE international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Givaki, Kamyar Hojabr, Reza Najafi, M. Hassan Khonsari, Ahmad Gholamrezayi, M. H. Gorgin, Saeid Rahmati, Dara Univ Tehran Sch Elect & Comp Engn Tehran Iran Univ Louisiana Lafayette Sch Comp & Informat Lafayette LA 70504 USA Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Shahid Beheshti Univ Fac Comp Sci & Engn Tehran Iran Iranian Res Org Sci & Technol IROST Tehran Iran

ISBN: (纸本)9781728116013

Inaccuracy of computations is an important challenge with Stochastic Computing (SC). Deterministic approaches are proposed to produce completely accurate results with SC circuits. Current deterministic methods need a large number of clock cycles to produce exact result. this directly translates to a very high energy consumption. We propose a method based on the Residue Number Systems (RNS) to mitigate the high processing time of the deterministic methods. Compared to the state-of-the-art deterministic methods of SC, our approach delivers 760x and 170x improvement in terms of processing time and energy consumption.

关键词： Clocks logic gates Computer architecture Cathode ray tubes Energy consumption Hardware Design automation

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Speeding-Up the Dynamic programming Procedure for the Edit Distance of Two Strings

Speeding-Up the Dynamic Programming Procedure for the Edit D...

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30th international conference on Database and Expert Systems Applications (DEXA)

作者： Lancia, Giuseppe Dalpasso, Marcello Univ Udine Dipartimento Sci Matemat Informat & Fis Via Sci 206 I-33100 Udine Italy Univ Padua Dipartimento Ingn Informaz Via Gradenigo 6-A I-35131 Padua Italy

ISBN: (纸本)9783030276843;9783030276836

We describe a way to compute the edit distance of two strings without having to fill the whole dynamic programming (DP) matrix, through a sequence of increasing guesses on the edit distance. If the strings share a certain degree of similarity, the edit distance can be quite smaller than the value of non-optimal solutions, and a large fraction (up to 80-90%) of the DP matrix cells do not need to be computed. Including the method's overhead, this translates into a speedup factor from 3x up to 30x in the time needed to find the optimal solution for strings of length about 20,000.

关键词： Dynamic programming

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PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations 30

PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Pr...

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30th IEEE international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Castaneda, Oscar Bobbett, Maria Gallyas-Sanhueza, Alexandra Studer, Christoph Cornell Univ Sch Elect & Comp Engn Ithaca NY 14850 USA

ISBN: (纸本)9781728116013

Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. We propose the Parallel Processor in Associative Content-addressable memory (PPAC), a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. the fully-digital nature of PPAC enables its implementation with standard-cell-based CMOS, which facilitates automated design and portability among technology nodes To demonstrate the efficacy of PPAC, we provide post-layout implementation results in 28nm CMOS for different array sizes. A comparison with recent digital and mixed-signal PIM accelerators reveals that PPAC is competitive in terms of throughput and energy-efficiency, while accelerating a wide range of applications and simplifying development.

关键词： Computer architecture throughput Sociology Statistics logic gates Program processors Task analysis

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FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation

FPGA Accelerator for Stereo Vision using Semi-Global Matchin...

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international conference on Field Programmable logic and Applications

作者： Shashwat Shrivastava Ziaul Choudhury Shashwat Khandelwal Suresh Purini Computer Systems Group International Institute of Information Technology Hyderabad India

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

In this paper, we propose a fully parallel and pipelined architecture for stereo vision on FPGAs using Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose this data parallelism through dependency relaxation. this establishes a trade-off between accuracy and throughput of the hardware. We tested the proposed architecture on Virtex-7 FPGA using KITTI 2012 and KITTI 2015 datasets. On images of resolution 1280x960, with 64 disparity levels, we are able to run our hardware design at 100 MHz. At this frequency, our design is able to process 322 frames per second which is 1.6 times faster than the state-of-the-art SGM implementation on FPGA. Our system can be scaled to a higher resolution image.

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Efficient Weight Reuse for Large LSTMs 30

Efficient Weight Reuse for Large LSTMs

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30th IEEE international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Que, Zhiqiang Nugent, thomas Liu, Shuanglong Tian, Li Niu, Xinyu Zhu, Yongxin Luk, Wayne Imperial Coll London Sch Engn Dept Comp London England Corerain Technol Ltd Shenzhen Peoples R China Chinese Acad Sci Shanghai Adv Res Inst Beijing Peoples R China

ISBN: (纸本)9781728116013

Long Short-Term Memory (LSTM) networks have been deployed in speech recognition, natural language processing and financial calculations in recent years, and are beginning to be used in systems where low latency and low power are required. To meet such requirements, we propose a stall-free hardware architecture by reorganising the order of operations in an LSTM system and develop a unique blocking-batching strategy to reuse the LSTM weights fetched from external memory to optimise the benefits of on-chip memory with a limited size for a large machine learning model. Evaluation results show that our architecture can achieve up to 20.8 GOPS/W, which would be among the highest for FPGA designs targeting LSTM systems with weights stored in off-chip memory. Comparing to the state-of-the-art design using off-chip memory to store the weights, we achieve 1.65 times higher performance-per-watt efficiency and 1.60 times higher performance-per-DSP efficiency. When compared with CPU and GPU implementation, our novel hardware architecture is 23.7 and 1.3 times faster while consuming 208 and 19.2 times lower energy respectively, which shows that our approach contributes to high performance and low power FPGA-based LSTM systems.

关键词： Computer architecture Field programmable gate arrays System-on-chip Microprocessors logic gates Hardware throughput

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Proving Properties of Sorting Programs: A Case Study in Horn Clause Verification 6

Proving Properties of Sorting Programs: A Case Study in Horn...

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30th international conference on Computer-Aided Verification (CAV) Held as Part of the Federated logic conference (FloC)

作者： De Angelis, Emanuele Pettorossi, Alberto Fioravanti, Fabio Proietti, Maurizio Univ G Annunzio Chieti Pescara DEC Viale Pindaro 42 I-65127 Pescara Italy Univ Roma Tor Vergata Via Politecn DICII Via Politecn 1 I-00133 Rome Italy CNR IASI Via Taurini 19 I-00185 Rome Italy

the proof of a program property can be reduced to the proof of satisfiability of a set of constrained Horn clauses (CHCs) which can be automatically generated from the pro-gram and the property. In this paper we have conducted a case study in Horn clause verification by considering several sorting programs with the aim of exploring the ef-fectiveness of a transformation technique which allows us to eliminate inductive data structures such as lists or trees. If this technique is successful, we derive a set of CHCs with constraints over the integers and booleans only, and the satisfiability check can often be performed in an effective way by using state-of-the-art CHC solvers, such as Eldarica or Z3. In this case study we have also illustrated the usefulness of a companion tech-nique based on the introduction of the so-called difference predicates, whose definitions correspond to lemmata required during the verification. We have considered functional programs which implement the following kinds of sorting algorithms acting on lists of integers: (i) linearly recursive sorting algorithms, such as insertion sort and selection sort, and (ii) non-linearly recursive sorting algorithms, such as quicksort and mergesort, and we have considered the following properties: (i) the partial correctness properties, that is, the orderedness of the output lists, and the equality of the input and output lists when viewed as multisets, and (ii) some arithmetic properties, such as the equality of the sum of the elements before and after sorting.

关键词： Integer programming

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A new method for computing stable models in logic programming 30

A new method for computing stable models in logic programmin...

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30th IEEE international conference on Tools with Artificial Intelligence (ICTAI)

作者： Khaled, Tarek Benhamou, Belaid Siegel, Pierre Aix Marseille Univ Univ Toulon CNRS LIS Marseille France

ISBN: (纸本)9781538674499

In this work, we introduce a new method for searching stable models of logical programs. this method is based on a relatively new semantics that has not been exploited yet. this semantics captures and extends that one of the stable models (Gelfond et al., 1988) and offers a new alternative to implement ASP solvers. the proposed method performs a DPLL enumerative process that is adapted to Answer Set programming (ASP) framework according to the used semantics. this method has the advantage to use a Horn clause representation having the same size as the input logic program has constant spatial complexity. It avoids the workload induced by the loop management from which suffer most of the ASP solvers based on the Clark completion. Moreover, the enumeration is done on a restricted set of literals called the strong back-door (STB) of the considered logic program. this reduces the algorithm time complexity which is in theory a function of the size of the STB set. We also introduced new inference rules that the method uses to prune its search tree and hence reduces its size in practice. We implemented the proposed method and applied it to enumerate the stable models of some combinatorial problems. the method is compared to other known systems and the obtained results show that our approach is a good alternative for designing ASP solvers.

关键词： Semantics Computational modeling logic programming Inference algorithms Time complexity

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Comparative Review of Approximate Multipliers

Comparative Review of Approximate Multipliers

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international conference on Radioelektronika

作者： Sushree Sila P. Goswami Bikram Paul Sunil Dutt Gaurav Trivedi Indian Institute of Technology Guwahati India

ISBN: (数字)9781728164694

ISBN: (纸本)9781728164700

In the digital signal processing (DSP) system, multiplier is a significant arithmetic module. It contributes mainly in the power consumption and speed, and efficient multipliers are the need of the hour. Approximate computing has added a unique dimension in the area of digital design by reducing area, power and delay. the demand of efficient approximate multipliers is enhancing due to the high speed and fault tolerance as well as its power efficiency. this paper presents comparison of few recent approximate multiplier designs. Experimental results based on the accuracy and circuit parameters are presented. the accuracy parameters are amplitude data accuracy (ACC_amp), information data accuracy (ACC_inf), error rate (ER) and mean error distance (MED). the circuit parameters are delay, power consumption, area. Based on these parameters, the best design in terms of power consumption and area is datapath complexity reduction approximate multiplier which exhibits 58% less power and 61% less area as compared to broken array multiplier.

关键词： logic gates Delays Power demand Adders Approximation algorithms Merging Error analysis

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Institute notes

Transactions of the South African Institute of Electrical En...

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Transactions of the South African Institute of Electrical Engineers 2021年第12期46卷 367-367页

the Council wishes to draw the attention of members to the international conference on Large Electric Systems (C.I.G.R.E.) which will hold its sixteenth session in Paris from the 30th May to the 9th June 1956.

关键词： Tin Storms Manufacturing logic gates Lightning Ionization High-voltage techniques

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