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30th IEEE international conference on Micro Electro Mechanical Systems (MEMS)

作者： Ilyas, Saad Jaber, Nizar Younis, Mohammad I. King Abdullah Univ Sci & Technol Phys Sci Div Thuwal Saudi Arabia

ISBN: (纸本)9781509050789

We present a reprogrammable Microelectromechanical systems (MEMS) logic device that can perform the fundamental logic gate AND, a universal logic gate NAND, and a tristate logic gate using mixed-frequency excitation. the concept is based on exciting combination resonances due to the mixing of two or more input signals. the device vibrates at two steady states;a high state when the combination resonance is activated and a low state when no resonance is activated. these vibration states are assigned to logical value 1 or 0 to realize these logic gates. Using AC signals to drive the resonator and to execute the logic inputs unifies the input and output wave forms of the logic device, thereby opening the possibility for cascading among logic devices. Moreover, the ability to perform these logic operations at any input frequency using frequency mixing techniques allows for overcoming the limitation of having a fixed operating frequency. these characteristics of such logic devices lay down the basis to achieve complex computing operations.

关键词： logic gates

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Magneto-Electric Magnetic Tunnel Junction Based Analog Circuit Options 30

Magneto-Electric Magnetic Tunnel Junction Based Analog Circu...

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30th IEEE international System-on-Chip conference (SOCC)

作者： Sharma, Nishtha Bird, Jonathan Dowben, Peter Marshall, Andrew Univ Texas Dallas Richardson TX 75083 USA Univ Buffalo Buffalo NY USA Univ Nebraska Lincoln NE USA

ISBN: (纸本)9781538640340

the magneto-electric magnetic tunnel junction (ME-MTJ) is a voltage controlled beyond CMOS device based on the principle of ME anti-ferromagnetic (AFM) exchange biasing of chromia (Cr2O3) and the tunneling magneto resistance (TMR) of a magnetic tunnel junction (fixed/free ferromagnet (FM) stack). these devices have previously been demonstrated for the implementation of digital logic and memory applications. We here demonstrate their analog capabilities with a variety of analog functions adapted specifically to the characteristics of ME-MTJ based devices. the novel circuit options proposed in this paper includes a ME-MTJ based analog comparator and the two variations of an 8 level analog-to-digital converter (ADC) using serial and parallel ME-MTJ circuit configurations.

关键词： Spintronics Magneto-Electric Magnetic Tunnel Junction (ME-MTJ) logic Memory Analog-to-Digital converter (ADC) Verilog-A Magnetic Tunnel Junction (MTJ)

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Constraint logic programming over Infinite Domains with an Application to Proof 30

Constraint Logic Programming over Infinite Domains with an A...

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30th Workshops on (Constraint) logic programming (WLP) / 24th international Workshop on Functional and (Constraint) logic programming (WFLP)

作者： Krings, Sebastian Leuschel, Michael Heinrich Heine Univ Dusseldorf Inst Informat Univ Str 1 D-40225 Dusseldorf Germany

We present a CLP(FD)-based constraint solver able to deal with unbounded domains. It is based on constraint propagation, resorting to enumeration if all other methods fail. An important aspect is detecting when enumeration was complete and if this has an impact on the soundness of the result. We present a technique which guarantees soundness in the following way: if the constraint solver finds a solution it is guaranteed to be correct;if the constraint solver fails to find a solution it can either return the result "definitely false" in case it knows enumeration was exhaustive, or "unknown" in case it was aborted. the technique can deal with nested universal and existential quantifiers. It can easily be extended to set comprehensions and other operators introducing new quantified variables. We show applications in data validation and proof.

关键词： Computer programming languages

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Formal Verification of Power Management logic with Mixed-Signal Domains 30

Formal Verification of Power Management Logic with Mixed-Sig...

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30th international conference on VLSI Design / 16th international conference on Embedded Systems (VLSID)

作者： Mandal, Sudipa Da Costa, Antonio Bruto Hazra, Aritra Dasgupta, Pallab Naware, Bhushan Chunduri, Rama Mohan Basu, Sanjib Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India Indian Inst Technol Madras Tamil Nadu India Intel Technol India Pvt Ltd Bangalore Karnataka India

ISBN: (纸本)9781509057405

System on Chip (SoC) designs today have a large number of power domains regulated by complex on-chip power management logic. the power management logic is primarily digital in nature, but it relies on analog components such as Low Dropout Regulators (LDO) and Phase-Locked Loops (PLL) for delivery of regulated voltages and clock frequencies. In low power designs, such analog components may also be powered down at times, and hence power domains are defined around modules containing these components. the digital brain of the power management logic must correctly consider the latencies of the analog components in the power management fabric while switching the power domains driven by these components. this is a task which has become extremely complex by virtue of the multitude of LDOs and PLLs in a modern integrated circuit, and the numerous domains that they drive. this paper presents, for the first time, a formal verification methodology for automatically generating the necessary assertions from an extended syntax of the Unified Power Format (UPF) and proving them on the power management logic using available industrial formal verification tools.

关键词： Phase locked loops Clocks Timing Fabrics Computer bugs Sequential analysis Voltage control

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IoT-Based Online Access Control System for Vehicles in Truck-Loading Fuels Terminals

IoT-Based Online Access Control System for Vehicles in Truck...

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international conference on Microelectronics, ICM

作者： Moatz M. Bahgat Hania H. Farag Bassem Mokhtar Communication and Electronics Department Alexandria University Alexandria Egypt

ISBN: (纸本)9781538681688;9781538681671

Nowadays, the world is moving towards the use of the "Future Internet" concepts. the emergence of the Internet of things (IoT) as a new Future Internet concept has led to a new wave of application potential which could play an important role in our daily life. the performance of existing applications may be improved greatly by applying IoT-enabling technologies efficiently. this paper presents a developed IoT-based access control system for vehicles passing through the entry and exit gates in Truck-Loading Fuels Terminals. the developed system follows a new design approach utilizing one of the most prominent IoT technologies, the Radio Frequency Identification (RFID), with its write capabilities. the novel design approach followed in developing the presented topic aims at offering enhanced system performance with regard to speed, security and allocated resources.

关键词： Access control Radiofrequency identification Servers logic gates Lead Central Processing Unit

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A Novel Power Reduction Technique Using Wire Multiplexing 30

A Novel Power Reduction Technique Using Wire Multiplexing

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30th IEEE international System-on-Chip conference (SOCC)

作者： Said, Mostafa Hassan, Hossam Kim, HyungWon Khamis, Mostafa Assiut Univ Dept Elect Engn Assiut Egypt Chungbuk Natl Univ Dept Elect Engn Cheongju 361763 South Korea Mentor Graph Egypt Cairo Egypt

ISBN: (纸本)9781538640340

Power consumption reduction is a very critical challenge in nowadays nanoscale circuits. In this paper, a new power reduction approach is demonstrated. this approach is originally based on the idea of TSV multiplexing in 3D-ICs where two or more signals can flow through one TSV instead of multiple TSVs. Based on that behavior, the possibility of power reduction of this circuit is discovered and its generalization to any wire, i.e., wire multiplexing, is detailed. Also, an analytical power model for this circuit is developed to predict its power consumption behavior. Further, and by means of Cadence-Spectre simulations on 65 nm technology and also using the developed analytical model, the power reduction of wire multiplexing technique could be proved and verified.

关键词： Integrated circuit modeling through-silicon vias Capacitance Power demand Wires logic gates Multiplexing

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Productive corecursion in logic programming

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thEORY AND PRACTICE OF logic programming 2017年第5-6期17卷 906-923页

作者： Komendantskaya, Ekaterina Li, Yue Heriot Watt Univ Edinburgh Midlothian Scotland

logic programming is a Turing complete language. As a consequence, designing algorithms that decide termination and non-termination of programs or decide inductive/ coinductive soundness of formulae is a challenging task. For example, the existing state-of-the-art algorithms can only semi-decide coinductive soundness of queries in logic programming for regular formulae. Another, less famous, but equally fundamental and important undecidable property is productivity. If a derivation is infinite and coinductively sound, we may ask whether the computed answer it determines actually computes an infinite formula. If it does, the infinite computation is productive. this intuition was first expressed under the name of computations at infinity in the 80s. In modern days of the Internet and stream processing, its importance lies in connection to infinite data structure processing. Recently, an algorithm was presented that semi-decides a weaker property -of productivity of logic programs. A logic program is productive if it can give rise to productive derivations. In this paper, we strengthen these recent results. We propose a method that semi-decides productivity of individual derivations for regular formulae. thus, we at last give an algorithmic counterpart to the notion of productivity of derivations in logic programming. this is the first algorithmic solution to the problem since it was raised more than 30 years ago. We also present an implementation of this algorithm.

关键词： Horn clauses (co) recursion (co) induction infinite term trees productivity

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A Practical Study of Control in Objected-Oriented-Functional-logic programming with Paisley 30

A Practical Study of Control in Objected-Oriented-Functional...

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30th Workshops on (Constraint) logic programming (WLP) / 24th international Workshop on Functional and (Constraint) logic programming (WFLP)

作者： Trancon y Widemann, Baltasar Lepper, Markus Ilmenau Univ Technol Ilmenau Germany Semant GmbH Aachen Germany

Paisley is an extensible lightweight embedded domain-specific language for nondeterministic pattern matching in Java. Using simple APIs and programming idioms, it brings the power of functional-logic processing of arbitrary data objects to the Java platform, without constraining the underlying object-oriented semantics. Here we present an extension to the Paisley framework that adds pattern-based control flow. It exploits recent additions to the Java language, namely functional interfaces and lambda expressions, for an explicit and transparent continuation-passing style approach to control. We evaluate the practical impact of the novel features on a real-world case study that reengineers a third-party open-source project to use Paisley in place of conventional object-oriented data query idioms. We find the approach viable for incremental refactoring of legacy code, with significant qualitative improvements regarding separation of concerns, clarity and intentionality, thus making for easier code understanding, testing and debugging.

关键词： pattern matching control flow embedded domain-specific language object orientation refactoring

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Comparison of the SET Sensitivity of Standard logic Gates Designed in 130 nm CMOS Technology 30

Comparison of the SET Sensitivity of Standard Logic Gates De...

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30th IEEE international conference on Microelectronics (MIEL)

作者： Andjelkovic, M. Kristic, M. Kraemer, R. IHP Technol Pk 25 D-15236 Frankfurt Oder Germany

ISBN: (纸本)9781538625637

this paper analyzes the sensitivity of live standard logic gates (AND, OR, INV, NAND and NOR) to Single Event Transients (SETS). All gates have been designed in IHP's 130 nm bulk CMOS technology. the analysis Was conducted with SPICE simulations, employing the current injection concept to model the SET effects. the SET sensitivity of the investigated logic gates was evaluated in terms of critical charge. For each logic gate, the dependence of the critical charge on the input logic levels, size of target gate and size of load gate was investigated. Obtained results have shown that it is possible to establish a simple linear model for estimating the critical charge as a function of the sizing factors of target and load gates, for all investigated logic gates and all combinations of input logic levels. the model provides very: good accuracy compared to the results obtained by SPICE simulations. Integrating the proposed model into a high-level SET evaluation tool would allow to reduce the number of required circuit-level simulations for evaluating the SET robustness of complex digital circuits composed of standard logic gates.

关键词： logic gates Integrated circuit modeling Semiconductor device modeling SPICE Standards Analytical models Sensitivity

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NORA: Algorithmic Balancing without Pre-charge to thwart Power Analysis Attacks 30

NORA: Algorithmic Balancing without Pre-charge to Thwart Pow...

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30th international conference on VLSI Design / 16th international conference on Embedded Systems (VLSID)

作者： Jayasinghe, Darshana Ignjatovic, Aleksandar Parameswaran, Sri Univ New South Wales Sch Comp Sci & Engn Kensington NSW Australia

ISBN: (纸本)9781509057405

Power analysis attacks use power dissipation to find the secret key of cryptographic devices. Two of the main techniques used as the countermeasures of power analysis attacks are masking and balancing. this paper considers countermeasures with balancing only. All balancing methods proposed so far require a pre-charge (or a pre-clear) state for all registers in which the logic is initialized to logic '1' (or to logic '0') so that equal Hamming distances (HD) and Hamming weights (HW) are maintained. Pre-charging and pre clearing add additional clock cycles to the encryption algorithm. In this paper, for the first time, we present an algorithmic balancing technique (referred to as NORA;No Pre-charge) which does not require the pre-charge/pre-clear stage. the proposed balancing technique is explained as a generalized block cipher balancing technique and an Advanced Encryption Standard (AES) circuit is implemented as an example. Correlation power analysis attacks were carried out against 600,000 traces and Normalized Inter Class Variance (NICV) was used as the leakage evaluation methodology. the resulting circuit is the only complete AES circuit, which can balance both Hamming weights and Hamming distances without pre-charging or pre-clearing while resisting variability effects such as path imbalances and process variations. the circuit only consumes 8.1 x resources when compared to an unprotected AES circuit implemented on a Xilinx Kintex7-325T FPGA.

关键词： Registers Power dissipation logic gates High definition video Algorithm design and analysis Encryption Ciphers

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