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检索条件"任意字段=30th International Conference on Logic Programming"

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Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar Arrays 30

Efficient Binary Basic Linear Algebra Operations on ReRAM Cr...

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30th international conference on VLSI Design / 16th international conference on Embedded Systems (VLSID)

作者： Bhattacharjee, Debjyoti Chattopadhyay, Anupam Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore

ISBN: (纸本)9781509057405

Fast downscaling of technology features in CMOS fabrication processes have resulted in numerous insurmountable challenges, which prompted researchers to explore alternative storage and computing technologies. Resistive RAM (ReRAM) is a promising non-volatile storage technology with high endurance, high retention capacity and compatibility with CMOS manufacturing flow. More importantly, ReRAM devices exhibit capability to perform logic operations and therefore, provides an excellent platform for in-memory computing paradigm. Several prominent arithmetic and data analytic applications have been mapped on ReRAM crossbar array so far. Along this line of research, we undertake, for the first time, the mapping of binary-valued matrix-vector operations for ReRAM crossbar array. these linear algebra operations form the key component of diverse applications ranging from graph mining, image processing to bio-informatics. We perform detailed design exploration to obtain an efficient mapping, demonstrate the working flow and finally, present the impact of crossbar dimensions on performance.

关键词： logic arrays Arrays Linear algebra Data analysis CMOS technology Resistive RAM Data mining

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Automated reasoning for the dialetheic logic RM3 30

Automated reasoning for the dialetheic logic RM3

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30th international Florida Artificial Intelligence Research Society conference, FLAIRS 2017

作者： Pelletier, Francis Jeffry Sutcliffe, Geoff Hazen, Allen P. Department Philosophy University of Alberta Canada Department Computer Science University of Miami United States

ISBN: (纸本)9781577357872

this paper describes a system for automated reasoning in the dialetheic logic RM3. A dialetheic logic allows formulae to be true, or false, or (differently from classical logic) both true and false, and the connectives are interpreted in terms of these three truth values. Consequently some inference rules of classical logic are invalid in RM3, and some theorems of classical logic are not theorems of RM3. An automated theorem prover for first-order RM3 has been developed, based on translations of RM3 formulae to classical first-order logic, and use of existing first-order reasoning systems to reason over the translated formulae. Examples and results are provided to highlight the differences between reasoning in RM3 and classical logic. Copyright © 2017, Association for the Advancement of Artificial Intelligence (***). All rights reserved.

关键词： Automation

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SiC Power MOSFETs: the Current Status and the Potential for Future Development 30

SiC Power MOSFETs: The Current Status and the Potential for ...

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30th IEEE international conference on Microelectronics (MIEL)

作者： Dimitrijev, S. Griffith Univ Griffith Sch Engn Nathan Qld 4111 Australia Griffith Univ Queensland Micro & Nanotechnol Ctr Nathan Qld 4111 Australia

ISBN: (纸本)9781538625637

this paper reviews the advantages and the current status of commercially available SiC power MOSFETs, followed by an analysis of future trends and the potential for future development. Specifically, the review shows the advantages of the recently commercialized trench MOSFET structure and the potential for integration with SiC Schottky diodes to create fast MOSFETs. the current issues and the potential for future improvements in terms of low channel-carrier mobility and threshold-voltage drifts are also discussed.

关键词： Silicon carbide Power dissipation Resistance logic gates Capacitance Schottky diodes Silicon

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Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry logic 30

Asynchronous Early Output Section-Carry Based Carry Lookahea...

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30th IEEE international conference on Microelectronics (MIEL)

作者： Balasubramanian, P. Dang, C. Maskell, D. L. Prasad, K. Nanyang Technol Univ Sch Elect & Elect Engn 50 Nanyang Ave Singapore 639798 Singapore Nanyang Technol Univ Sch Comp Sci & Engn 50 Nanyang Ave Singapore 639798 Singapore Auckland Univ Technol Dept Elect & Elect Engn Auckland 1142 New Zealand

ISBN: (纸本)9781538625637

A new asynchronous early output section-carry based carry lookahead adder (SCBCLA) with alias cam, output logic is presented in this paper. To evaluate the proposed SCBCLA With alias carry logic and to make a comparison with other CLAs, a 32-bit addition operation is considered. Compared to the weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with alias logic reports a 13% reduction in area without any increases in latency and power dissipation. On the other hand, in comparison with the early output recursive CLA (RCLA). the proposed early output SCBCLA with alias logic reports a 16% reduction in latency while occupying almost the same area and dissipating almost the same average power. All the asynchronous CLAs are quasi-delay-insensitive designs which incorporate the delay-insensitive dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking. the adders were realized and the simulations were performed based on a 32/28nm CMOS process.

关键词： Asynchronous circuits Encoding Wires logic gates Timing Adders

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MCMLSD: A Dynamic programming Approach to Line Segment Detection 30

MCMLSD: A Dynamic Programming Approach to Line Segment Detec...

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30th IEEE/CVF conference on Computer Vision and Pattern Recognition (CVPR)

作者： Almazan, Emilio J. Tal, Ron Qian, Yiming Elder, James H. Nielsen Madrid Spain Uber Technol San Francisco CA USA York Univ Toronto ON Canada

ISBN: (纸本)9781538604571

Prior approaches to line segment detection typically involve perceptual grouping in the image domain or global accumulation in the Hough domain. Here we propose a probabilistic algorithm that merges the advantages of both approaches. In a first stage lines are detected using a global probabilistic Hough approach. In the second stage each detected line is analyzed in the image domain to localize the line segments that generated the peak in the Hough map. By limiting search to a line, the distribution of segments over the sequence of points on the line can be modeled as a Markov chain, and a probabilistically optimal labelling can be computed exactly using a standard dynamic programming algorithm, in linear time. the Markov assumption also leads to an intuitive ranking method that uses the local marginal posterior probabilities to estimate the expected number of correctly labelled points on a segment. To assess the resulting Markov Chain Marginal Line Segment Detector (MCMLSD) we develop and apply a novel quantitative evaluation methodology that controls for under-and over-segmentation. Evaluation on the YorkUrbanDB dataset shows that the proposed MCMLSD method outperforms the state-of-the-art by a substantial margin.

关键词： Image segmentation Image edge detection Markov processes Probabilistic logic Uncertainty Training Dynamic programming

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Quasi-topological structure of extensions in logic of determination of objects (LDO) for typical and atypical objects 30

Quasi-topological structure of extensions in logic of determ...

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30th international Florida Artificial Intelligence Research Society conference, FLAIRS 2017

作者： Desclés, Jean-Pierre Pascu, Anca Biskri, Ismail Université de Paris-Sorbonne France Université de Brest France Université de Québec à Trois-Rivières Canada

ISBN: (纸本)9781577357872

this paper introduces and discusses a new algebraic structure, the quasi-topologic structure. the idea of this structure comes from language analysis on the one hand and from analysis of some real situations of clustering on the other. From the cognitive point of view, it is related to the logic of Determination of Objects (LDO) and to the logic of Typical and Atypical Objects (LTA) which is particular case of LDO. From the mathematical point of view, it is related to topology. By introducing the notion of internal and external border, it extends the notion of border from classical topology.

关键词： Topology

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Process Parameters Variations Influence on CMOS IC's Hardness to total Ionizing Dose 30

Process Parameters Variations Influence on CMOS IC's Hardnes...

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30th IEEE international conference on Microelectronics (MIEL)

作者： Moskovskaya, Y. M. Nikiforov, A. Y. Bobrovskiu, D. V. Ulanova, A. V. Zhukov, A. A. NRNU MEPhI Inst Extremal Appl Elect Moscow Russia SMC Technol Ctr Moscow Russia

ISBN: (纸本)9781538625637

the influence of 1,5 urn Rad-hard CMOS process parameters (gate oxide growth temperature and chemical environment) variations on the total ionizing dose effects is comparatively analyzed in experiment on the build-in test structures. the optimal process parameter set is found as a compromise between IC functionality and radiation hardness.

关键词： Integrated circuits Power supplies Standards logic gates Temperature sensors CMOS process Microelectronics

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Capacitance Model for MOSFET Operated in all Regions 30

Capacitance Model for MOSFET Operated in all Regions

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30th IEEE international conference on Microelectronics (MIEL)

作者： Benfdila, A. Lakhlef, A. Univ M Mammeri Microelect & Nanotechnol Res Grp GRMNT Tizi Ouzou Algeria

ISBN: (纸本)9781538625637

the present paper deals with the modeling of the capacitance of a MOSFET operated in all regions, i.e., subthreshold linear and saturation. the model is based on the electric charges behavior under a dynamic gate biasing and relies on our current we developed earlier. the proposed model has been compared with the classical model and found to be in a good agreement in linear and saturation regions. In addition, our model expresses the capacitance in the subthreshold region which is described by the classical model. the experimental data obtained on research devices are found to suite our model in all the three regions.

关键词： Mathematical model logic gates Capacitance Data models Semiconductor device modeling Current measurement threshold voltage

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Investigation on Cylindrical Gate-All-Around (GAA) Tunnel FETS Scaling 30

Investigation on Cylindrical Gate-All-Around (GAA) Tunnel FE...

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30th IEEE international conference on Microelectronics (MIEL)

作者： Kessi, M. Benfdila, A. Lakhlef, A. Univ M Mammeri Fac Elect Engn & Comp Sci MNRG Tizi Ouzou 15000 Ummto Dz Algeria

ISBN: (纸本)9781538625637

the present work deals with the study and investigation on the GAA Tunnel PET electrical parameters under varying physical conditions, especially, channel thickness t(si) and length. as Well as oxide thickness t(ox). Moreover, the effect of the channel doping concentration and the gate work function Phi(m), this is achieved using the finite element, numerical method by solving Poisson's equation in the cylindrical coordinate system. the work aims better device performances and fast switching with lower costs.

关键词： logic gates Performance evaluation Electron devices Doping Transconductance Mathematical model threshold voltage

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A Systematic Study on the Hysteresis Behaviour and Reliability of MoS₂ FET 30

A Systematic Study on the Hysteresis Behaviour and Reliabili...

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30th international conference on VLSI Design / 16th international conference on Embedded Systems (VLSID)

作者： Meersha, Adil Sathyajith, B. Shrivastava, Mayank Indian Inst Sci Dept Elect Syst Engn Bangalore 560012 Karnataka India

ISBN: (纸本)9781509057405

For reliable use of Molybdenum Disulfide (MoS2) FETs in ULSI applications device reliability issues like hysteresis behaviour and non idealities must be well understood and mitigated. In this work, we present unique hysteresis behaviour in the I-V characteristics of few layer MoS2 FETs. Root cause and physics behind the hysteresis behaviour has been explored by repeated experiments under various electrical, temperature, pressure, and environmental conditions. A trap based theory is proposed considering the device behaviour in different conditions and these observations give insight towards device passivation and choosing the right dielectric for reliable utilization of MoS2 FETs.

关键词： Hysteresis logic gates Molybdenum Sulfur Reliability Temperature measurement Voltage measurement

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