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检索条件"任意字段=30th International Conference on Logic Programming"

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Parameterized free space redistribution for engineering change in placement of integrated circuits

Parameterized free space redistribution for engineering chan...

引用

IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Taraneh Taghavi Shyam Ramji Frank Musante Suhasini Rege IBM San Diego CA USA IBM Hopewell Junction NY USA IBM Bangalore India

In this paper we present a method for parameterized free space redistribution of a fragmented placement. the fragmentation problem arises in different contexts within the physical design automation, including post physical synthesis for filler cell insertion, incremental placement, timing optimization, and late mode ECO fix-ups. To address this problem, we apply a post-placement parameterized method of defragmentation. this method involves capturing a view of a given placement and modeling a dynamic programming problem to optimally maximize the amount of so-called useful free space as defined by a given set of parameters. the parameters act as constraints to preserve the row placement and order of the cells while minimizing the perturbation of the whole design for a successful timing and design closure. Experimental results demonstrate that by applying the proposed technique, on average, 9.7% increase in the number of inserted filler cells and 5.7% improvement in the success rate of incremental placement requests can be achieved with minimal or no impact on timing and wirelength. Moreover, when deployed in early mode buffering for timing optimization, this technique can result in 3% reduction in the number of paths with negative slacks.

关键词： Timing logic gates Optimization Planning Arrays Dynamic programming Algorithm design and analysis

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Human operator trust in autonomic functionalities 12

Human operator trust in autonomic functionalities

引用

30th European conference on Cognitive Ergonomics, ECCE 2012

作者： Liinasuo, Marja Karvonen, Hannu Aaltonen, Iina Fuentes, Beatriz Castro, Alfonso VTT Technical Research Centre of Finland Vuorimiehentie 3 Espoo 02044 VTT Finland Telefónica I+D l Ronda de la Comunicación s/n 28050 Madrid Spain

ISBN: (纸本)9781450317863

Motivation - To shed light on the conceptions of human network operators about autonomic functionalities and the determinants of trust regarding future autonomic networks. Research approach - An interview study with 33 human operators at non-managerial level was performed. the interview consisted of 19 questions related to various aspects of autonomic functionalities. Findings/Design - Several components of trust and distrust for autonomic functionalities were found. Distrust based on assumed failure of the functionalities was the most prominent negative feature. the possibility to concentrate on more demanding tasks was the most surprising positive feature. Research limitations/Implications - Only 33 human operators from two telecom companies participated in the study, which limits the possible generalisation of the findings. Originality/Value - the research makes a contribution to the scarce amount of publications on human aspect in telecommunication domain. Take away message - Trust-related factors can be used for identifying and extracting general requirements for future tools from the user point of view. Copyright 2012 ACM.

关键词： Computer programming

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Fast error aware model for arithmetic and logic circuits

Fast error aware model for arithmetic and logic circuits

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Samy Zaynoun Muhammad S. Khairy Ahmed M. Eltawil Fadi J. Kurdahi Amin Khajeh Electrical Engineering and Computer Science Department University of California Irvine Irvine CA USA INTEL Research Laboratory Hillsboro OR USA

As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. this paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability.

关键词： Propagation delay logic gates Delay Integrated circuit modeling Vectors Table lookup

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Non-enumerative generation of statistical path delays for ATPG

Non-enumerative generation of statistical path delays for AT...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Ahish Mysore Somashekar Spyros Tragoudas Sreenivas Gangadhar Rathish Jayabharathi ECE Department Southem Illinois University Carbondale IL USA Intel Folsom CA USA

A Monte Carlo based approach capable of identifying the probability distributions that describe the delay of every sensitizable path in a path implicit manner is proposed. It is shown experimentally that the statistical information for all paths is generated as fast as the traditional Monte Carlo simulation that identifies the probability density function for the circuit delay.

关键词： Delay Monte Carlo methods Data structures USA Councils Probability distribution logic gates Circuit faults

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A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic

A stochastic reconfigurable architecture for fault-tolerant ...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Peng Li Weikang Qian David J. Lilja Department of Electrical and Computer Engineering University of Minnesota Minneapolis USA University of Michigan Shanghai Jiaotong University Joint Institute Shanghai China

Computation performed on stochastic bit streams is less efficient than that based on a binary radix because of its long latency. However, for certain complex arithmetic operations, computation on stochastic bit streams can consume less energy and tolerate more soft errors. In addition, the latency issue could be solved by using a faster clock frequency or in combination with a parallel processing approach. To take advantage of this computing technique, previous work proposed a combinational logic-based reconfigurable architecture to perform complex arithmetic operations on stochastic streams of bits. In this paper, we enhance and extend this reconfigurable architecture using sequential logic. Compared to the previous approach, the proposed reconfigurable architecture takes less hardware area and consumes less energy, while achieving the same performance in terms of processing time and fault-tolerance.

关键词： Computer architecture Polynomials Multiplexing Image coding Streaming media Silicon Clocks

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Studying interaction with documentation: Methodological lessons learned in two semi-naturalistic designs 12

Studying interaction with documentation: Methodological less...

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30th European conference on Cognitive Ergonomics, ECCE 2012

作者： Van Loggem, Brigit Open University Netherlands

ISBN: (纸本)9781450317863

Semi-naturalistic research designs allow for studying behaviour in a realistic setting, achieving a fair degree of ecological validity without the disadvantages of purely naturalistic designs. A semi-naturalistic study sets boundaries for the behaviour under investigation, within which respondents still act freely. In order to allow for between-subjects comparisons, the raw data obtained must be structured, either through pre-structuring or through post-structuring. Motivation - there exists little methodological guidance in the field of documentation design. Qualitative and quantitative studies alike are carried out using an amalgam of methods that were developed for other disciplines. this paper contributes to awareness of the pitfalls (but also the benefits) of doing so. Research approach - this paper considers two seminaturalistic studies into interaction with software and documentation from a methodological point of view. In the first, the data was collected in the respondents' workplace and then poststructured. In the second, the data was collected in a laboratory setting and pre-structured through the use of an observation tool. Findings/Design - Both methods are described in some detail, followed by a discussion of methodological issues discovered after the design had been executed. Finally, the relative advantages and disadvantages of the two approaches are highlighted. Take-away message - Documentation design can fruitfully combine methodological approaches originally developed for other disciplines, provided these are adapted for the purpose with care and discretion. Copyright 2012 ACM.

关键词： Computer programming

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Description logic knowledge base exchange 6th

Description logic knowledge base exchange

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6th international conference on Web Reasoning and Rule Systems, RR 2012

作者： Botoeva, Elena KRDB Research Centre Free Univ. of Bozen-Bolzano Piazza Dominicani 3 Bolzano39100 Italy

ISBN: (纸本)9783642332029

Data exchange is a field of database theory that deals with transferring data between differently structured databases, with motivation coming from industry [21,17]. the starting point of intensive investigation of the problem of data exchange was given in [14] where it was defined as, given data structured under a source schema and a mapping specifying how it should be translated to a target schema, to transform the source data into data structured under the target schema such that it accurately reflects the source data w.r.t. the mapping. this problem has been studied for different combinations of languages used to specify the source and target schema, and the mappings [8]. Most of the results in the literature consider tuple generating dependencies (tgds) as the language to specify mappings. Tgds allow one to express containment of conjunctive queries, and have been widely employed in other areas of database theory. Furthermore, once a target instance is materialized, one mightwant to perform query answering over it.

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Understanding variance propagation in stochastic computing systems

Understanding variance propagation in stochastic computing s...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Chengguang Ma Shunan Zhong Hua Dang School of Information and Electronics Beijing Institute of Technology Beijing China

Stochastic arithmetic provide several benefits over traditional computing method such as high fault tolerance, simple hardware implementation, low hardware area. In order to increase accuracy of error analysis and improve method of performance evaluation for stochastic computing systems, a new variance transfer function for stochastic computing systems based on combinational logic is proposed in this work. the transfer function is proved by a new mathematical method: hypergeometric decomposition, which makes stochastic computing theory more perfect and reliable. According to the variance transfer function, several measurements based on variance are developed to evaluate performance between different stochastic computing algorithms. By comparing this method with traditional bit-level simulation method, variance measurements are proved to be less time consumption, more comprehensive, and more effective to evaluate and understand stochastic computing systems.

关键词： Mathematical model Transfer functions Algorithm design and analysis Equations Streaming media logic gates Computational modeling

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Automatic assertion extraction in gate-level simulation using GPGPUs

Automatic assertion extraction in gate-level simulation usin...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Shohei Ono Takeshi Matsumoto Masahiro Fujita Department of Electrical Engineering and Information System University of Tokyo Tokyo Japan VLSI Design and Education Center University of Tokyo Tokyo Japan VLSI Design and Education Center JST CREST University of Tokyo Tokyo Japan

In modern VLSI designs, assertions play an important role to understand design intention and ensure correctness of designs. In this paper, we consider to generate assertions from simulation results. this assertion extraction is performed by examining whether a logical relation is satisfied among a set of signals. We propose to accelerate it by utilizing a highly parallelized computation performed by GPGPUs. through the experiments with designs from industry, our implementation on GPGPU runs 30 times faster than a software implementation.

关键词： Simulation Silicon logic gates Very large scale integration Graphics processing units Central Processing Unit Educational institutions

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An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits

An efficient reliability simulation flow for evaluating the ...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Mehdi Kamal Qing Xie Massoud Pedram Ali Afzali-Kusha Saeed Safari School of Electrical and Computer Engineering University of Tehran Iran Department of Electrical Engineering-Systems University of Southern California USA

Hot carrier injection (HCI) effect is one of the major reliability concerns in VLSI circuits. this paper presents a scalable reliability simulation flow, including a logic cell characterization method and an efficient full chip simulation method, to analyze the HCI-induced transistor aging with a fast run time and high accuracy. the transistor-level HCI effect is modeled based on the Reaction-Diffusion (R-D) framework. the gate-level HCI impact characterization method combines HSpice simulation and piecewise linear curve fitting. the proposed characterization method reveals that the HCI effect on some transistors is much more significant than the others according to the logic cell structure. Additionally, during the circuit simulation, pertinent transitions are identified and all cells in the circuit are classified into two groups: critical and non-critical. the proposed method reduces the simulation time while maintaining high accuracy by applying fine granularity simulation time steps to the critical cells and coarse granularity ones to the non-critical cells in the circuit.

关键词： Human computer interaction Integrated circuit modeling logic gates Capacitance MOSFETs Semiconductor device modeling

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