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检索条件"任意字段=30th International Conference on Logic Programming"

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Hierarchical modeling of Phase Change memory for reliable design

Hierarchical modeling of Phase Change memory for reliable de...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Zihan Xu Ketul B. Sutaria Chengen Yang Chaitali Chakrabarti Yu Cao School of ECEE Arizona State University Tempe AZ USA

As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. this work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.

关键词： Phase change random access memory Integrated circuit modeling Reliability Geometry thermal resistance programming

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Memory module-level testing and error behaviors for phase change memory

Memory module-level testing and error behaviors for phase ch...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Zhe Zhang Weijun Xiao Nohhyun Park David J. Lilja Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA Department of Electrical and Computer Engineering Virginia Commonwealth University Richmond VA USA

Phase change memory (PCM) is a promising technology to solve energy and performance bottlenecks for memory and storage systems. To help understand the reliability characteristics of PCM devices, we present a simple fault model to categorize four types of PCM errors. Based on our proposed fault model, we conduct extensive experiments on real PCM devices at the memory module level. Numerical results uncover many interesting trends in terms of the lifetime of PCM devices and error behaviors. Specifically, PCM lifetime for the memory chips we tested is greater than 14 million cycles, which is much longer than for flash memory devices. In addition, the distributions for four types of errors are quite different. these results can be used for estimating PCM lifetime and for measuring the fabrication quality of individual PCM memory chips.

关键词： Phase change materials programming Interference Resistance Error analysis

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A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance

A novel variation-tolerant 4T-DRAM cell with enhanced soft-e...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Shrikanth Ganapathy Ramon Canal Dan Alexandrescu Enrico Costenaro Antonio Gonzalez Antonio Rubio Department dArquitectura de Computadors Universitat Poliltècnica de Catalunya Barcelona Spain Engineering Division IRoC Technologies SA Grenoble France Department dEnginyeria Electrònica Universitat Poliltècnica de Catalunya Barcelona Spain

In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. the retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment.

关键词： logic gates Transistors Random access memory threshold voltage Capacitance System-on-a-chip Power demand

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Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs

Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate ...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Zoran Jaksic Ramon Canal Department of Computer Architecture Universitat Poliltècnica de Catalunya Barcelona Spain

In this paper, we present the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post-fabrication/run-time adaptability.

关键词： Computer architecture Microprocessors Random access memory logic gates FinFETs Delay

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Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening

Timing aware partitioning for multi-FPGA based logic simulat...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Subramanian Poothamkurissi Swaminathan Pey-Chang Kent Lin Sunil P. Khatri Department of ECE Texas A and M University College Station TX USA

In order to accelerate logic simulation, it is highly beneficial to simulate the circuit design on FPGA hardware. this is often referred to as emulation, and we use the terms simulation and emulation interchangeably in this paper. However, limited hardware on FPGAs prevents large designs from being implemented on a single FPGA. Hence there is a need to partition the design and simulate it on a multi-FPGA platform. In contrast to existing FPGA-based post-synthesis partitioning approaches which first completely flatten the circuit and then possibly perform bottom-up clustering, we perform a selective top-down flattening and thereby avoid the potential netlist blowup. this also allows us to preserve the design hierarchy to guide the partitioning and to make subsequent debugging easier. Our approach analyzes the hierarchical design and selectively flattens instances using two metrics based on slack. the resulting partially flattened netlist is converted to a hypergraph, partitioned using hMetis, and reconverted back to a plurality of FPGA netlists, one for each FPGA of the FPGA-based accelerated logic simulation platform. We compare our approach with a partitioning approach that operates on a completely flattened netlist. Static timing analysis was performed for both approaches, and over 15 large examples from the OpenCores project, our approach yields a 52% logic simulation speedup and about 0.74× runtime for the entire flow, compared to the completely flat approach. the entire tool chain of our approach is automated in an end-to-end flow from hierarchy extraction, selective flattening, partitioning, and netlist reconstruction. Compared to an existing method which also performs slack-based partitioning of a hierarchical netlist, we obtain a 35% simulation speedup. Our method scales very well, yielding a significantly better simulation speedup and runtime improvement for larger examples.

关键词： Partitioning algorithms Field programmable gate arrays Algorithm design and analysis Runtime Delay Mathematical model

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A flexible structure of standard cell and its optimization method for near-threshold voltage operation

A flexible structure of standard cell and its optimization m...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Shinichi Nishizawa Tohru Ishihara Hidetoshi Onodera Graduate School of Informatics Kyoto University Japan CREST Japan Science and Technology Agency Sakyo Kyoto Japan

With ever growing demands of mobile devices, low power consumption has become essential for VLSI circuits. Since standard cell libraries are typically used in many parts of VLSI circuits, their performance has a strong impact on realizing high speed and low power VLSI circuits. One of the most promising approaches for reducing the power consumption of the circuit is lowering the supply voltage. However this causes an increase of imbalance between rise and fall delays especially for cells having transistor stacks. For mitigating this imbalance, this paper proposes a structure of standard cells where the P/N ratio of each cell can be independently customized for near-threshold operation in VLSI circuits. the structure cancels the imbalance between rise and fall delays at the expense of cell area. the experiments with ISCAS'85 benchmark circuits demonstrate that the standard cell library consisting of the proposed cells reduces the power consumption of the benchmark circuits by 16% on average without increasing the circuit area, compared to that of the same circuit synthesized with a library which is not optimized for the near-threshold operation.

关键词： Standards Libraries Delay logic gates Optimization Transistors MOS devices

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Maximizing crosstalk-induced slowdown during path delay test

Maximizing crosstalk-induced slowdown during path delay test

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Dibakar Gope D. M. H. Walker Department of Electrical and Computer Engineering University of Wisconsin-Madison Madison WI USA Department of Computer Science Texas A and M University College Station TX USA

In this paper, we present a timing-driven test generator to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. the framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. the test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. the proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.

关键词： Delay Crosstalk Couplings Compaction Automatic test pattern generation logic gates

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Oblivious routing design for mesh networks to achieve a new worst-case throughput bound

Oblivious routing design for mesh networks to achieve a new ...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Guang Sun Chia-Wei Chang Bill Lin Lieguang Zeng University of California San Diego USA State Key Laboratory on Microwave and Digital Communications Tsinghua National Laboratory for Information Science and Technology Department of Electronic Engineering Tsinghua University Beijing China

1/2 network capacity is often believed to be the limit of worst-case throughput for mesh networks. However, this paper provides a new worst-case throughput bound, which is higher than 1/2 network capacity, for odd radix two-dimensional mesh networks. In addition, we propose a routing algorithm called U2TURN that can achieve this worst-case throughput bound for odd radix meshes. For even radix meshes, we prove that U2TURN achieves the optimal worst-case throughput, namely, half of network capacity. U2TURN considers all routing paths with at most 2 turns and distributes the traffic loads uniformly in both X and Y dimensions. theoretical analysis and simulation results show that U2TURN outperforms existing routing algorithms in worst-case throughput. Moreover, U2TURN achieves good average-throughput at the expense of approximately 1.5× minimal average hop count. For asymmetric meshes, we further propose an algorithm called “U2TURN-A” and provide theoretical analysis for different algorithms. Both theoretical analysis and simulation show that U2TURN and U2TURN-A outperform existing algorithms VAL, DOR and O1TURN in both worst-case and average throughput for asymmetric meshes.

关键词： throughput Routing Algorithm design and analysis Mesh networks Measurement Approximation algorithms Linear programming

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Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

Flash correct-and-refresh: Retention-aware error management ...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Yu Cai Gulay Yalcin Onur Mutlu Erich F. Haratsch Adrian Cristal Osman S. Unsal Ken Mai DSSC Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA Barcelona Supercomputing Center Barcelona Spain LSI Corporation Allentown PA USA

With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. the goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. the key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46× average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.

关键词： Error correction codes Flash memory Bit error rate threshold voltage Nonvolatile memory programming

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Evolving a storage block endurance classifier for Flash memory: A trial implementation

Evolving a storage block endurance classifier for Flash memo...

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IEEE international conference on Cybernetic Intelligent Systems, CIS

作者： Damien Hogan Tom Arbuckle Conor Ryan Computer Science and Information Systems University of Limerick Ireland

Solid State Drives (SSDs) have a number of significant advantages over traditional Hard Disk Drives (HDDs) but are currently far more expensive and have smaller capacities. these drives are based on NAND Flash memory devices, which have limited working lives. the number of times locations in such devices can be successfully programmed before they become unreliable is termed their endurance. there is currently no way to estimate accurately when a location within a Flash device will fail, so manufacturers give extremely conservative guarantees about the number of program operations their chips can endure. this paper describes a trial implementation of Genetic programming (GP) used to evolve a Binary Classifier that predicts whether storage blocks within Flash memory devices will still be functioning correctly beyond some predefined number of cycles. the classifier is supplied with only the measured program and erase times from a relatively early point in the lifetime of a block. Using the relationships between these times, the system can accurately predict whether the block will continue to function satisfactorily up to a required number of cycles. Experiments on test sets comprised of unseen data show that our classifier obtains up to an average of 95% accuracy across 30 runs.

关键词： Flash memories logic gates Timing Testing Hardware Sociology Statistics

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