the author describes a fuzzy-logic-based tuner for continuous online tuning of proportional, integral, and derivative (PID) controllers. A unique feature of this tuner is the adaptive scaling of its output in real-tim...
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the author describes a fuzzy-logic-based tuner for continuous online tuning of proportional, integral, and derivative (PID) controllers. A unique feature of this tuner is the adaptive scaling of its output in real-time by a self-monitoring algorithm which is a function of the history and certain statistical measures of performance. the adaptive scaling makes the tuner robust to large variations in parametric and dynamic uncertainties in the plant models. the author presents simulation results to demonstrate the performance of the tuner and the self-monitoring algorithm.< >
A completed software product is the end result of many decisions that must be made throughout the development lifecycle. Unfortunately, the rationale for these decisions is usually not captured and is therefore lost. ...
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A completed software product is the end result of many decisions that must be made throughout the development lifecycle. Unfortunately, the rationale for these decisions is usually not captured and is therefore lost. the Software Using RATionale (SEURAT) system integrates withthe Eclipse Interactive Development Environment to support rationale capture and use. In addition to presenting the rationale to the developer/maintainer as needed, SEURAT also supports requirements traceability and impact assessment.
this paper introduces and investigates a configurable source coupled logic (cSCL) by configuring the bulk connection of the PMOS load transistor. In the low-power mode configuration, the circuit operates in weak inver...
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ISBN:
(纸本)9781538681688;9781538681671
this paper introduces and investigates a configurable source coupled logic (cSCL) by configuring the bulk connection of the PMOS load transistor. In the low-power mode configuration, the circuit operates in weak inversion (i.e. subthreshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its drain. However, in the highspeed mode configuration, the circuit operates in strong inversion (i.e. above threshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its source. We have designed a 3-input XOR gate using the standard CMOS, STSCL, SCL, and cSCl using a 65 nm CMOS technology. Simulations demonstrated that, by configuring the cSCL in the low-power mode, it can operate up to 4X faster than standard CMOS and by configuring the cSCL in the high-speed, it can provide a power reduction of 62.46% compared to the standard CMOS.
In federated and pervasive networks, trust management has become a cornerstone for information security and privacy. Although people have recognized the importance of privacy and security for their personal informatio...
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In federated and pervasive networks, trust management has become a cornerstone for information security and privacy. Although people have recognized the importance of privacy and security for their personal information, they remain uncertain when they have to define and enforce their own access control rules or have to handle indirect information. Indirect information and subjective judgment are the major sources of uncertainty in federated trust management. this paper introduces fuzzy logic into the definition and evaluation of trust, and then provides a formal representation of fuzzy rules. It also offers a set of derivation rules for analyzing and reasoning among fuzzy rules in order to enforce these rules with a certain level of uncertainty. Application of this model to a healthcare environment with pervasive computing devices across trust domains provides a new method to handle uncertainty in trust management for federated and pervasive networks
As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. this paper presents an error aware model for arithmetic and logic...
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As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. this paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability.
In October 2004 the University of Lugano in southern Switzerland established a new faculty of informatics. Its founding principles are innovation in teaching and faculty participation in the research community. With r...
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In October 2004 the University of Lugano in southern Switzerland established a new faculty of informatics. Its founding principles are innovation in teaching and faculty participation in the research community. With respect to teaching, students spend mornings attending lectures and afternoons in an Atelier designed to support interaction both among students and withthe instructors. In teaching the first year "programming Fundamentals" courses, we took advantage of the clean slate nature of the faculty to introduce innovative teaching elements. the novel aspects include our use of Scheme, Smalltalk, and Java, our combination of individual, pair and group projects and the integration of expert lectures to introduce useful, but slightly orthogonal elements at key points in the semester. Our very positive experience is reported along with a discussion of aspects to improve in the future.
this book constitutes the refereed proceedings of the 14thinternationalconference on Foundations of Software Science and computational Structures, FOSSACS 2011, held in Saarbrücken, Germany, March 26—April 3, ...
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ISBN:
(数字)9783642198052
ISBN:
(纸本)9783642198045
this book constitutes the refereed proceedings of the 14thinternationalconference on Foundations of Software Science and computational Structures, FOSSACS 2011, held in Saarbrücken, Germany, March 26—April 3, 2011, as part of ETAPS 2011, the European Joint conferences on theory and Practice of Software.
the 30 revised full papers presented together with one full-paper length invited talk were carefully reviewed and selected from 100 submissions. the papers are organized in topical sections on coalgebra and computability, type theory, process calculi, automata theory, semantics, binding, security, and program analysis.
the newly envisioned semantic Web contains as a component what may be called a Web of Trust, consisting of the trust relationships held between its participants. In terms of this, the degree to which participant A bel...
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the newly envisioned semantic Web contains as a component what may be called a Web of Trust, consisting of the trust relationships held between its participants. In terms of this, the degree to which participant A believes what is believed by participant B depends on the degree to which A trusts B. this paper presents a formal language with well-defined semantics within which such a participant (or agent) can express the relevant conditions of belief and trust, and outlines some key techniques for reasoning withthese expressions. Novel in this treatment is the use of linguistic, rather than numeric, measures of belief. the aim in this is to make the language and reasoning system more intuitive for the human user. Also novel is an explicit delineation of the context within which the language and reasoning techniques are to be applied
In this work, Q-learning technique on level of optimization is used to improve the performance of handover parameters such as handover margin (HOM) and time to trigger (TTT) and evaluated in terms of total system dela...
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ISBN:
(纸本)9781538681688;9781538681671
In this work, Q-learning technique on level of optimization is used to improve the performance of handover parameters such as handover margin (HOM) and time to trigger (TTT) and evaluated in terms of total system delay, average number of handover and system throughput in purpose to provide long term evolution (LTE) technology seamless and fast handover from one cell to another, knowing that optimization is based on Q-learning technique which achieves minimum average number of handover per user and also have maximum throughput than the literature work of optimization using fuzzy logic optimization.
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