Service oriented architecture (SOA) is an architectural style to reuse and integrate existing systems for designing new applications. Each application is designed in an implementation independent manner using two majo...
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Service oriented architecture (SOA) is an architectural style to reuse and integrate existing systems for designing new applications. Each application is designed in an implementation independent manner using two major abstract concepts: services and connections between services. In SOA, the non-functional aspects (e.g., security and fault tolerance) of services and connections should be described separately from their functional aspects (i.e., business logic) because different applications use services and connections in different non-functional contexts. this paper presents a UML profile to graphically describe and maintain non-functional aspects in SOA in an implementation independent manner. this paper also describes how the proposed profile is used to develop secure service-oriented applications
Summary form only given, as follows. Recently, a new type of headlamp for automobiles called HID (high intensity discharge) lamp is widely used. HID lamp has some advantages (low wattage, high efficacy, white color, a...
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Summary form only given, as follows. Recently, a new type of headlamp for automobiles called HID (high intensity discharge) lamp is widely used. HID lamp has some advantages (low wattage, high efficacy, white color, and long life) compared with general halogen lamp.
this work proposes a machine learning approach for cell characterization of logic gates. Traditional electrical simulation-based characterization faces challenges related to foundry secrecy and runtime. the proposed f...
this work proposes a machine learning approach for cell characterization of logic gates. Traditional electrical simulation-based characterization faces challenges related to foundry secrecy and runtime. the proposed framework addresses these challenges by using machine learning models to estimate power consumption and propagation times. the experiments demonstrate the potential of the framework to predict different logic gate functions in different technology models, showing the feature extraction differences for bulk complementary metal–oxide–semiconductor, CMOS, and fin field-effect transistor, FinFET, devices. the results demonstrate the effectiveness of the Decision Tree algorithm in fast and accurate prediction of cell behavior, with inference times almost a thousand times faster than the traditional electrical simulation and a higher coefficient of determination than 95%.
this paper describes an approach to constructing control barrier functions that realize planning and control objectives that are expressed in a fragment of signal temporal logic. the particular construction is based o...
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ISBN:
(数字)9781665406734
ISBN:
(纸本)9781665406741
this paper describes an approach to constructing control barrier functions that realize planning and control objectives that are expressed in a fragment of signal temporal logic. the particular construction is based on the navigation function method for robot motion planning and is attractive because it offers a straightforward way to design the robot control law that implements the signal temporal logic specification. the efficacy of the reported method is illustrated through simulation examples.
We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) withthread-level speculation (TLS) suppor...
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We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) withthread-level speculation (TLS) support. CMPs have low sharing and communication costs relative to traditional multiprocessors, and thread-level speculation (TLS) support. CMPs have low sharing and communication costs relative to traditional multiprocessors, and thread-level speculation (TLS) simplifies program parallelization by allowing us to parallelize optimistically without violating correct sequential program behavior. Using a Java virtual machine with dynamic compilation support coupled with a hardware profiler, speculative buffer requirements and inter-thread dependencies of prospective speculative thread loops (STLs) are analyzed in real-time to identify the best loops to parallelize. Once sufficient data has been collected to make a reasonable decision, selected loops are dynamically recompiled to run in parallel. Experimental results demonstrate that Jrpm can exploit thread-level parallelism with minimal effort from the programmer. On four processors, we achieved speedups of 3 to 4 for floating point applications, 2 to 3 on multimedia applications, and between 1.5 and 2.5 on integer applications. Performance was achieved by automatic selection of thread decompositions by the hardware profiler, intra-procedural optimizations on code compiled dynamically into speculative threads, and some minor programmer transformations for exposing parallelism that cannot be performed automatically.
Software engineering is developing very fast. To keep up withthe changes, software companies need effective methods of knowledge transfer. In the paper a 3-step approach to knowledge transfer, called Technical Drama,...
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Software engineering is developing very fast. To keep up withthe changes, software companies need effective methods of knowledge transfer. In the paper a 3-step approach to knowledge transfer, called Technical Drama, is presented. the paper is focused on transferring knowledge concerning architecture evaluation, but the approach could also be applied to transferring knowledge concerning inspections, testing etc. It is claimed in the paper that the Technical Drama can be useful in the industrial context (two case studies are described) as well as at university (then a kind of software studio is required).
In a deregulated electricity market, the most important purpose of each generating company (GENCO) is to find its optimal bid at each trading period. this paper proposes a new algorithm to determine optimal prices and...
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ISBN:
(纸本)9781509027064
In a deregulated electricity market, the most important purpose of each generating company (GENCO) is to find its optimal bid at each trading period. this paper proposes a new algorithm to determine optimal prices and quantities for the GENCO using a new context named dominating demand. the proposed method considers transmission constraints as a determining factor to construct optimal bids. the method is appropriate to be used for a GENCO in the complex system due to its simplicity. Finally, dominating demand and the optimal bid is calculated for modified IEEE 30-bus system in order to approve method's transparent application.
Computation performed on stochastic bit streams is less efficient than that based on a binary radix because of its long latency. However, for certain complex arithmetic operations, computation on stochastic bit stream...
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Computation performed on stochastic bit streams is less efficient than that based on a binary radix because of its long latency. However, for certain complex arithmetic operations, computation on stochastic bit streams can consume less energy and tolerate more soft errors. In addition, the latency issue could be solved by using a faster clock frequency or in combination with a parallel processing approach. To take advantage of this computing technique, previous work proposed a combinational logic-based reconfigurable architecture to perform complex arithmetic operations on stochastic streams of bits. In this paper, we enhance and extend this reconfigurable architecture using sequential logic. Compared to the previous approach, the proposed reconfigurable architecture takes less hardware area and consumes less energy, while achieving the same performance in terms of processing time and fault-tolerance.
An equivalent circuit model for gallium nitride-based high electron mobility transistors (GaN-HEMTs) in an exact circuit simulation is proposed. the equivalent circuit contains inherent GaN device properties, such as ...
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An equivalent circuit model for gallium nitride-based high electron mobility transistors (GaN-HEMTs) in an exact circuit simulation is proposed. the equivalent circuit contains inherent GaN device properties, such as current-collapse and shot-channel effects. Base on the equivalent model, an power loss simulator was developed. the simulation accuracy was more than 93%. A converter optimum design method is discussed using the power loss simulator.
the jGRASP lightweight IDE provides object viewers that automatically generate dynamic, state-based visualizations of objects and primitive variables in Java. Multiple synchronized visualizations of an object, includi...
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the jGRASP lightweight IDE provides object viewers that automatically generate dynamic, state-based visualizations of objects and primitive variables in Java. Multiple synchronized visualizations of an object, including complex data structures, are immediately available to users from the jGRASP debugger window or object workbench. Initial use has demonstrated the object viewers' potential as an aid to understanding and debugging
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