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检索条件"任意字段=32nd ACM International Symposium on Field-Programmable Gate Arrays, FPGA 2024"

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A 475 MHz Manycore fpga Accelerator for RTL Simulation 24

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Kashani, Sahand Emami, Mahyar Kamahori, Keisuke Pourghannad, Sepehr Raj, Ritik Larus, James R. Epfl Lausanne Switzerland University of Washington Seattle United States Georgia Tech Atlanta United States

ISBN: (纸本)9798400704185

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large fpga. Implementing manycore accelerators on fpgas is challenging as designers must reconcile the conflicting goals of maximizing the number of cores on the chip and clocking them at the highest possible frequency. Designers face two classes of constraints: (1) architectural constraints imposed by a large fpga's multi-die structure, and (2) physical constraints imposed by the fpga shell's size and placement. Physical design therefore plays a critical role in the implementation of manycore accelerators. We present physical design challenges faced during Manticore's implementation on the AMD Alveo U200 card - -a large fpga with a poorly-placed, wide shell that challenges physical implementation. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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fpga 2024 - Proceedings of the 2024 acm/SIGDA international symposium on field programmable gate arrays

FPGA 2024 - Proceedings of the 2024 ACM/SIGDA International ...

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

ISBN: (纸本)9798400704185

The proceedings contain 23 papers. The topics discuss include: CompressedLUT: an open-source tool for lossless compression of lookup tables for function evaluation and beyond;MiCache: an MSHR-inclusive non-blocking cache design for fpgas;Hardcaml MSM: a high-performance split CPU-fpga multi-scalar multiplication engine;DynaRapid: from C to fpga in a few seconds;design and implementation of a primary visual cortex pathway model based on opponent-process theory;Hardcaml: an OCaml hardware domain-specific language for efficient and robust design;XUNI: virtual machine abstraction for self-contained and multi-tenant cloud fpgas;ISO-TENANT: rethinking fpga power distribution network (PDN): a hardware based solution for remote power side channel attacks in fpga;and accelerating autonomous path planning on fpgas with sparsity-aware HW/SW co-optimizations.

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From Topology to Realization in fpga/VPR Routing 24

From Topology to Realization in FPGA/VPR Routing

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Abbaszadeh, Mahdi How, Dana L. RapidSilicon Los GatosCA United States

ISBN: (纸本)9798400704185

Versatile Place and Route (VPR) enabled the exploration of diverse fpga architectures. Openfpga extended VPR through bitstream generation and added silicon compilation. Our work is one of several efforts to use this combination to build commercial devices, which, to achieve competitiveness, has necessitated several improvements to routing and elsewhere for area, power, and performance. Fitting to the MCNC and VTR benchmarks using this work, our first improved routing pattern yields a 22% reduction in metal loading, a 14% reduction in routing multiplexer input pin count per function tile, and a 10% reduction in source to farthest sink paths. For this, routed length increased 5%, the proportion of net detours increased 11%, router heap operations increased 16%, and router iterations increased 42%, as the unmodified VPR router worked harder on routing with fewer switches but without introducing any routing failures. This work provides the first steps to a routing compiler for Openfpga/VPR, much as ASIC/SoC flows use a memory compiler. © 2024 acm.

关键词： field programmable gate arrays (fpga)

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Hardcaml MSM: A High-Performance Split CPU-fpga Multi-Scalar Multiplication Engine 24

Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar...

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Ray, Andy Devlin, Benjamin Quah, Fu Yong Yesantharao, Rahul Jane Street London United Kingdom Jane Street New York City United States

ISBN: (纸本)9798400704185

This paper presents a split CPU-fpga Multi-Scalar Multiplication (MSM) engine written in Hardcaml. Hardcaml MSM was submitted to the 2022 ZPrize cryptography competition and won 1st place in the fpga track. Hardcaml MSM targets the BLS12-377 elliptic curve and is currently the lowest-latency implementation utilizing fpgas published. For a MSM of order 2^26 we achieve a single-round MSM latency of 5.518s and average power of 52W, with our design running at 278MHz. When performing multiple rounds of MSM with the same base points but random scalars, we are able to further mask host I/O and memory latency and reduce latency to 5.083s. This is a latency improvement of 13% over the previously fastest reported fpga solution, and an improvement of 472% when compared to state of the art open-source CPU library gnark-crypto. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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A Statically and Dynamically Scalable Soft GPGPU 24

A Statically and Dynamically Scalable Soft GPGPU

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Langhammer, Martin Constantinides, George A. Intel Corporation Imperial College London United Kingdom Imperial College London United Kingdom

ISBN: (纸本)9798400704185

Current soft processor architectures for fpgas do not utilize the potential of the massive parallelism available. fpgas now support many thousands of embedded floating point operators, and have similar computational densities to GPGPUs. Several soft GPGPU or SIMT processors have been published, but the reported large areas and modest Fmax makes their widespread use unlikely for commercial designs. In this paper we take an alternative approach, building the soft GPU microarchitecture around the fpga resource mix available. We demonstrate a statically scalable soft GPGPU processor (where both parameters and feature set can be determined at configuration time) that always closes timing at the peak speed of the slowest embedded component in the fpga (DSP or hard memory), with a completely unconstrained compile into a current Intel Agilex fpga. We also show dynamic scalability, where a subset of the thread space can be specified on an instruction-by-instruction basis. For one example core type, we show a logic range - depending on the configuration - of 4k to 10k ALMs, along with 24 to 32 DSP Blocks, and 50 to 250 M20K memories. All of these instances close timing at 771 MHz, a performance level limited only by the DSP Blocks. We describe our methodology for reliably achieving this clock rate by matching the processor pipeline structure to the physical structure of the fpga fabric. We also benchmark several algorithms across a range of data sizes, and compare to a commercial soft RISC processor. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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Low-Latency, Line-Rate Variable-Length field Parsing for 100+ Gb/s Ethernet 24

Low-Latency, Line-Rate Variable-Length Field Parsing for 100...

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Stitt, Greg Piard, Wesley Crary, Christopher University of Florida GainesvilleFL United States

ISBN: (纸本)9798400704185

field-programmable gate arrays (fpgas) are widely employed in network-interface cards across applications including cloud services, machine learning, and high-frequency trading. These applications often share a common optimization goal: minimizing latency while meeting throughput constraints. In addition, these applications ideally aim to achieve "line-rate"operation, where the fpga operates at full bandwidth without using back-pressure to stall incoming data. However, these goals are often conflicting. For example, to minimize latency, application protocols must effectively utilize network bandwidth by encoding variable-length data in variable-length fields. However, variable-length fields often have prohibitively complex processing requirements that prevent line-rate throughput or have excessive latency. In this paper, we present a novel variable-length field parser capable of scaling to accommodate the bus widths and clock frequencies necessary for 100+ Gb/s Ethernet, while still achieving low latency. Our experiments demonstrate parsing variable-length fields at line rate for anticipated bus widths and throughputs, achieving ultra-low latencies under 2 ns for some use cases. To the best of our knowledge, this latency surpasses existing work, including fixed-length field parsing. © 2024 acm.

关键词： Bandwidth

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REFINE: Runtime Execution Feedback for INcremental Evolution on fpga Designs 24

REFINE: Runtime Execution Feedback for INcremental Evolution...

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Park, Dongjoon Dehon, André University of Pennsylvania PhiladelphiaPA United States

ISBN: (纸本)9798400704185

fpga design optimization is challenging for developers for two main reasons. First, developers cannot easily identify a bottleneck of the design to know where to focus optimization effort to improve the application execution time. Second, slow, monolithic fpga compilation makes evaluation of each design change costly. Together, these make fpga development different and more challenging than traditional software development where software engineers are accustomed to using rich profiling tools to improve their designs through a series of quick, incremental refinements. To address these issues, we propose a fast bottleneck identification scheme using runtime feedback and separate fpga compilation. Our scheme systematically identifies bottlenecks in streaming computations based on FIFO event counters extracted from hardware execution and guides developers to the operations that limit performance. We showcase our support for bottleneck identification with the fast, automatic design space exploration, iterating initial design points quickly with a separate, incremental compilation strategy. When the design reaches the point that latency cannot improve with the separate compilation approach, we migrate to the monolithic design flow that does not have the area overhead and communication bandwidth limit of separate compilation approach. Then, the remaining design space, if any, is explored with a monolithic flow. When tested on the AMD ZCU102 embedded platform with realistic HLS dataflow designs, our approach correctly identifies bottlenecks improving application latency 2.2-12.7× while reducing tuning time by 1.3-2.7× compared to monolithic flow. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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An fpga-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits 24

An FPGA-Enabled Framework for Rapid Automated Design of Phot...

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Xu, Zhenyu Yu, Miaoxiang Cai, Jillian Gafsi, Saddam Ryckman, Judson Douglas Yang, Qing Wei, Tao University of Rhode Island KingstonRI United States Clemson University ClemsonSC United States

ISBN: (纸本)9798400704185

This paper introduces an fpga-enabled framework to accelerate the automated design process for Photonic Integrated Circuit (PIC) devices. PICs are foreseen as a foundation for the next-generation semiconductors. However, the complexity of PIC design presents considerable challenges. Machine Learning (ML) techniques have shown promise in the realm of PIC design. The primary hurdle, however, is the extended training duration, solely constrained by the slow electromagnetic (EM) Finite-Difference Time-Domain (FDTD) solver. We propose a fast framework with a dedicated fpga FDTD accelerator tailor-designed to speed up the PIC simulation. Benchmarking was carried out against commercial tools, with the single-fpga accelerator outperforming both a multicore CPU and a GPU cluster. We taped out and evaluated the PIC devices designed through the proposed framework, and the experimental outcomes aligned. This demonstrates the full design circle, showcasing that the proposed framework enabled by fpga breaks the current bottleneck in this domain. This study was conducted entirely on a commercial cloud platform (AWS), leveraging CPUs, fpgas, and GPUs, with fpga programming efficiently executed using High-Level Synthesis (HLS) and the Xilinx Runtime (XRT). The fpga, along with its modern development tools, is seamlessly integrated into a heterogeneous computing platform, showcasing the accessible and practical nature of this approach. Our findings show the exciting possibility that ML-based physical design could be notably sped up enabled by fpgas in a cloud-hosted heterogeneous cluster as a service. © 2024 acm.

关键词： field programmable gate arrays (fpga)

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SuperNIC: An fpga-Based, Cloud-Oriented SmartNIC 24

SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Lin, Will Shan, Yizhou Kosta, Ryan Krishnamurthy, Arvind Zhang, Yiying University of California San Diego San DiegoCA United States University of Washington Seattle WA United States

ISBN: (纸本)9798400704185

With CPU scaling slowing down in today's data centers, more functionalities are being offloaded from the CPU to auxiliary devices. One such device is the SmartNIC, which is being increasingly adopted in data centers. In today's cloud environment, VMs on the same server can each have their own network computation (or network tasks) or workflows of network tasks to offload to a SmartNIC. These network tasks can be dynamically added/removed as VMs come and go and can be shared across VMs. Such dynamism demands that a SmartNIC not only schedules and processes packets but also manages and executes offloaded network tasks for different users. Although software solutions like an OS exist for managing software-based network tasks, such software-based SmartNICs cannot keep up with the quickly increasing data-center network speed. This paper proposes a new SmartNIC platform called SuperNIC that allows multiple tenants to efficiently and safely offload fpga-based network computation DAGs. For efficiency and scalability, our core idea is to group network tasks into virtual chains that are dynamically mapped to different forms of physical chains depending on load and fpga space availability. We further propose techniques to automatically scale network task chains with different types of parallelism. Moreover, we propose a fair sharing mechanism that considers both fair space sharing and fair time sharing of different types of hardware resources. Our fpga prototype of SuperNIC achieves high bandwidth and low latency performance whilst efficiently utilizing and fairly sharing resources. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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Quickloop: An efficient, fpga-accelerated exploration of parameterized DNN accelerators 32

Quickloop: An efficient, FPGA-accelerated exploration of par...

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32nd international Conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Mahmood, Tayyeb Inayat, Kashif Chung, Jaeyong Incheon Natl Univ Incheon South Korea Barcelona Supercomp Ctr Barcelona Spain

ISBN: (纸本)9798350342543

Quickloop is a design-space exploration (DSE) framework of parameterized RTL generators, their software stack, and their simulation on fpga. fpgas are recently accelerating RTL simulations due to their rapid turnaround times (TAT), compared to ASIC. However, this TAT is still restrictive in DSE. We adopt a data-driven approach to optimize Quickloop's TAT and leverage this framework to extensively search the design space of an open source DNN accelerator. We show that our approach effectively slashes the TAT by above 30%, compared to conventional toolflow.

关键词： field programmable gate arrays (fpga)

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