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检索条件"任意字段=32nd International Conference on Field-Programmable Logic and Applications, FPL 2022"

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Proceedings - 2022 32nd international conference on field-programmable logic and applications, fpl 2022

Proceedings - 2022 32nd International Conference on Field-Pr...

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32nd international conference on field-programmable logic and applications, fpl 2022

ISBN: (纸本)9781665473903

The proceedings contain 77 papers. The topics discussed include: BunchBloomer: cost-effective bloom filter accelerator for genomics applications;ultra-flow: an ultra-fast and high-quality optical flow accelerator with deep feature matching on FPGA;virtualization of reconfigurable mixed-criticality systems;tram: an open-source template-based reconfigurable architecture modeling framework;a flexible real-time stereo vision architecture for multiple data streams with runtime configurable parameters;optimized mappings for symmetric range-limited molecular force calculations on FPGAs;the design method of logic circuits based on the voltage-input enhanced scouting logic gates;reducing FPGA memory footprint of stencil codes through automatic extraction of memory patterns;model-based generation of hardware/software architectures for robotics systems;and direct device-to-device physical page migrations in multi-FPGA shared virtual memory systems.

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fpl Demo: FPGA Bitstream Virus Scanning 32

FPL Demo: FPGA Bitstream Virus Scanning

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32nd international conference on field-programmable logic and applications (fpl)

作者： Powell, Joseph Matas, Kaspar Manev, Kristiyan Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

The expansion of the FPGA into complex market sectors imposes new demands on the security model of the devices. This demonstration shows off a series of tools developed to decode and scan the contents of a bitstream f... 详细信息

ISBN: (纸本)9781665473903

关键词： field programmable gate arrays (FPGA)

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fpl Demo: logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation 32

FPL Demo: Logic Shrinkage: A Neural Architecture Search-Base...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Auffret, Marie Wang, Erwei Davis, James J. Imperial Coll London Dept Elect & Elect Engn London England AMD Mountain View CA USA

ISBN: (纸本)9781665473903

logic shrinkage is an open-source, state-of-the-art neural architecture search (NAS)-based approach to the automated design of DNN inference accelerators that ideally suit FPGA deployment [1], [2]. Where NAS traditionally sees candidate functions such as convolutions automatically evaluated and selected between to form a network, logic shrinkage operates at ultra-fine granularity, resulting in a netlist of LUTs as the topology. Our results for datasets of complexity ranging from MNIST to ImageNet show area and energy efficiency gains vs binary neural networks (BNNs) of up to 6 x and lOx. © 2022 IEEE.

关键词： Shrinkage

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fpl Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs 32

FPL Demo: SERVE: Agile Hardware Development Platform with Cl...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Wang, Zelin Zhang, Ke Chang, Yisong Yin, Yanlong Chen, Yuxiao Zhao, Ran Wang, Songyue Chen, Mingyu Bao, Yungang Chinese Acad Sci State Key Lab Processor ICT Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781665473903

We introduce SERVE, a cloud platform for agile hardware software co-design, with cloud IDE and cloud FPGAs integrated. SERVE enables users to focus on logic designs, without facing the hassle of setting up FPGA tools and development environment. Users can write and simulate hardware logic in the cloud IDE and then generate bitstream files through a Continuous Integration (CI) pipeline. Finally, the bitstream files are deployed on an FPGA board. A great amount of testbenches will be executed to ensure the correctness of the hardware logic. We will demo a workflow of modifying a RISC-V processor and getting the design change quickly evaluated using SERVE.

关键词： field programmable gate arrays (FPGA)

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The Design Method of logic Circuits based on the Voltage-Input Enhanced Scouting logic Gates 32

The Design Method of Logic Circuits based on the Voltage-Inp...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Liu, Fan Zhang, Sunrui Cui, Xiaole Peking Univ Shenzhen Grad Sch Key Lab Integrated Microsyst Shenzhen Peoples R China Peng Cheng Lab Shenzhen Peoples R China

ISBN: (纸本)9781665473903

The Enhanced Scouting logic (ESL) is a memristive logic gate family with low sensitivity to resistance variation and high device endurance. This work studies the design methods of logic circuits based on the Voltage-Input Enhanced Scouting logic (VIESL) gates. Both the single-array and dual-array synthesis methods are proposed. The read/write separation technique of VIESL gates facilitates the pipelined logic operations. The synthesis results on the benchmarks show that the circuit generated by the proposed single-array synthesis method has the best performance compared with that of its counterparts, and the dual-array synthesis method reduces the cell counts effectively.

关键词： RRAM Enhanced Scouting logic logic synthesis read/write separation pipeline

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fpl Demo: 400G FPGA Packet Capture Based on Network Development Kit 32

FPL Demo: 400G FPGA Packet Capture Based on Network Developm...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Cabal, Jakub Sikora, Jiri Friedl, Stepan Spinler, Martin Korenek, Jan CESNET Ale Zikova 4 Prague 16000 Czech Republic

ISBN: (纸本)9781665473903

CESNET, the Czech NREN (National Research and Education Network), has a long research history in the area of high-speed network monitoring using FPGA accelerated cards. Now, we are ready to present our open-source Network Development Kit for FPGAs1, which is ready for 400 Gbps data transfers via Ethernet and PCI Express. The demo aims to show the possibilities of ndK, which allows users to quickly and easily develop new network applications for FPGA-based acceleration cards. Even high-speed DMA Module fully supported in ndK is available free of charge for academic purposes. It can thus significantly contribute to the spread of 400G technology in the academic community and also among other users. The accelerator card equipped with the Intel Agilex I-Series FPGA will transmit and receive back 400G Ethernet (400GBASE) traffic via external loopback. The received packets will be forwarded via very fast packet DMA transfers directly to the RAM of the host computer.

关键词： field programmable gate arrays (FPGA)

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Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA 32

Ultra-Flow: An Ultra-fast and High-quality Optical Flow Acce...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Ling, Yehua Yan, Yuanxing Huang, Kai Chen, Gang Sun Yat Sen Univ Sch Comp Sci & Engn Guangzhou Guangdong Peoples R China Peng Cheng Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781665473903

Dense and accurate optical flow estimation is an important requirement for dynamic scene perception in autonomous systems. However, most of the existing FPGA accelerators are based on classic methods, which cannot deal with large displacements of moving objects in ultra-fast scenes. In this paper, we present Ultra-Flow, an ultra-fast pipelined architecture for efficient optical flow estimation and refinement. Ultra-Flow utilizes binary neural networks to generate the robust feature map, on which hierarchical matching is directly performed. Therefore, multiple usages of neural networks at hierarchical levels can be avoided to achieve hardware efficiency in Ultra-Flow. Optimizations, including local flow regularization and enhanced matching, are further used to improve the throughput and refine the optical flow to obtain higher accuracy. Evaluation results show that, compared to state-of-the-art FPGA accelerators, Ultra-Flow achieves leading accuracy in the Middlebury sequences at ultra-fast processing speed up to 687.92 frames/s for 640x 480 pixel images.

关键词： field programmable gate arrays (FPGA)

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TRAC: Compilation-based Design of Transformer Accelerators for FPGAs 32

TRAC: Compilation-based Design of Transformer Accelerators f...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Plagwitz, Patrick Hannig, Frank Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Nurnberg Germany

ISBN: (纸本)9781665473903

Transformer-type Neural Networks (NNs) have shown impressive accuracy numbers in Natural Language Processing (NLP) applications where Recurrent Neural Networks (RNNs) have been in use before, even surpassing them. However, differing considerably from common types of NNs, existing accelerator designs, particularly for field-programmable Gate Arrays (FPGAs), cannot be used to implement them. Previous research has shown FPGAs to be platforms superior to CPUs and even GPUs for accelerating NNs when it comes to energy efficiency. Following the development of automated compiler-based design flows for NNs, there is still a lack of such an approach for transformers and FPGA targets. In this realm, this paper presents a novel compiler called TRAC as well as a library of operators and modules for implementing transformer accelerators on FPGAs. Based on optimization and code generation settings in the compiler using an integrated approach combining weight compression techniques with according adaptations of the accelerator modules, a design space of accelerators is defined and explored. For each design, a system-level data path and control unit architecture is generated, which integrates module-level designs using hierarchical High-Level Synthesis (HLS). We evaluate our implementation for the BERT network and provide results regarding the trade-off between execution time, accuracy, and FPGA resource usage.

关键词： field programmable gate arrays (FPGA)

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FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs 32

FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs

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32nd international conference on field-programmable logic and applications (fpl)

作者： Zhang, Peng Zhang, Shijun Li, Shang Zhang, Jin Liu, Shaoxun Bu, Youjun Southeast Univ Sch Cyber Sci & Engn Nanjing Peoples R China Purple Mt Labs Endogenous Safety & Secur Res Ctr Nanjing Peoples R China Natl Digital Switching Engn & Technol Res Ctr Zhengzhou Peoples R China

ISBN: (纸本)9781665473903

Accelerating regular expression (regex) matching, or equivalently finite automata processing, using FPGAs is widely adopted by many demanding regex-based applications to improve throughput and power efficiency. However, offloading a large regex rule set entirely into an FPGA is expensive, if not unaffordable, due to the limited on-chip resources. In this paper, we propose FRA-FPGA (Fast Reconfigurable Automata on FPGAs), a homogeneous NFA architecture on FPGAs which can be reconfigured within 1 mu s. Meanwhile, the reconfiguration time of FRA-FPGA is independent of the number of regex rules it accommodates. Because FRA-FPGA can be reloaded quickly, it is feasible to offload the small subset of activated regex rules into FRA-FPGA dynamically, as opposed to compiling the whole regex rule set into FPGA beforehand. We implemented FRA-FPGA on the Xilinx U200 card to accelerate Hyperscan. Our experimental results show that the FRA-FPGA can improve Hyperscan's throughput by about 15 times (stream mode) and 33 times (block mode), respectively, while consuming only 4.23% logic resources and 16.64% memory resources of the FPGA(VU9P).

关键词： field programmable gate arrays (FPGA)

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DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks 32

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DS...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Sommer, Jan Oezkan, M. Akif Keszocze, Oliver Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg D-91054 Erlangen Germany

ISBN: (纸本)9781665473903

The number of Digital Signal Processor (DSP) resources available in field programmable Gate Arrays (FPGAs) is often quite limited. Therefore, full utilization of available DSP resources for the computationally intensive parts of an algorithm is paramount for optimizing the non-functional properties of an implementation (i.e., performance, power, and area). The DSPs available in Xilinx devices implement large bit width operators (i.e. a 48-bit accumulator or a 18 x 27 multiplier). However, using such a DSP for low-precision quantized data (as is common in image processing or machine learning applications) leaves the DSP resources underutilized. As a remedy, a method has been proposed to pack and compute four 4-bit multiplications on a single DSP in a single clock cycle. This paper presents a generalization of this scheme to arbitrary bit widths and number of multiplications. We also demonstrate that the previously proposed approach leads to errors (Mean Absolute Error (MAE) = 0.37). Furthermore, we explain where these errors come from and how they can be corrected. On top, we introduce a novel approximate method called "Overpacking" which allows to squeeze even more multiplications into a single DSP at the cost of small errors (MAE = 0.47). Overpacking allows to squeeze six 4-bit multiplications into a single DSP compared to just four in the literature. Finally, we introduce an alternative method for packing multiple small-bit width additions into a single 48-bit accumulator for use in applications such as Spiking Neural Networks.

关键词： Digital Signal Processing (DSP) field-programmable Gate Array (FPGA) Approximate Computing

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