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检索条件"任意字段=32nd International Conference on Field-Programmable Logic and Applications, FPL 2022"

共 49 条记录，以下是21-30 订阅

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The Design Method of logic Circuits based on the Voltage-Input Enhanced Scouting logic Gates

The Design Method of Logic Circuits based on the Voltage-Inp...

引用

international conference on field programmable logic and applications

作者： Fan Liu Sunrui Zhang Xiaole Cui Key Lab of Integrated Microsystems Peking University Shenzhen Graduate School Shenzhen China Peng Cheng Lab Shenzhen China

The Enhanced Scouting logic (ESL) is a memristive logic gate family with low sensitivity to resistance variation and high device endurance. This work studies the design methods of logic circuits based on the Voltage-Input Enhanced Scouting logic (VIESL) gates. Both the single-array and dual-array synthesis methods are proposed. The read/write separation technique of VIESL gates facilitates the pipelined logic operations. The synthesis results on the benchmarks show that the circuit generated by the proposed single-array synthesis method has the best performance compared with that of its counterparts, and the dual-array synthesis method reduces the cell counts effectively.

关键词： Resistance Sensitivity Design methodology logic gates Benchmark testing logic functions logic arrays

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Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches

Optimizing Application Mapping for Multi-FPGA Systems with M...

引用

international conference on field programmable logic and applications

作者： Kohei Ito Ryota Yasudo Hideharu Amano Dept. of Information and Computer Science Keio University Japan Graduate School of Informatics Kyoto University Japan

Multi-FPGA systems have received an attention as a computing cluster for multi-access edge computing (MEC). Also, they can process time-critical jobs with their hardwired logic. For this purpose, the static time-division multiplexing (STDM) network is adopted because it enables to predict latency and bandwidth. However, the overall performance of the STDM network depends on the number of time slots. This paper proposes a new mapping tool that optimizes the application mapping so that the number of slots is minimized. Our tool handles multicasts and multi-ejection function which are effective techniques for STDM switches implemented on an FPGA cluster. For applications with all-to-all communication, our experimental results show that the tool reduces the number of time slots by 59–68% with both multicasts and multi-ejection switches.

关键词： Multiplexing Multi-access edge computing Bandwidth Time factors Optimization field programmable gate arrays

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HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation

HiPR: High-level Partial Reconfiguration for Fast Incrementa...

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international conference on field programmable logic and applications

作者： Yuanlong Xiao Aditya Hota Dongjoon Park André DeHon Dept. of Electrical and Systems Engineering University of Pennsylvania Philadelphia PA USA

Partial Reconfiguration (PR) is a key technique in the design of modern FPGAs. However, current PR tools heavily rely on the developers to manually conduct PR module definition, floorplanning, and flow control at a low level. The existing PR tools do not consider High-Level-Synthesis languages either, which is of great interest to software developers. We propose HiPR, an open-source framework, to bridge the gap between HLS and PR. HiPR allows the developer to define partially reconfigurable C/C++ functions instead of Verilog modules, which benefits the FPGA incremental compilation and automates the flow from C/C++ to bitstreams. By mapping Rosetta HLS benchmarks, the incremental compilation can be accelerated by 3–10× compared with Xilinx Vitis normal flow without performance loss.

关键词： Benchmark testing Software Hardware design languages field programmable gate arrays

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Tunable Fine-grained Clock Phase-shifting for FPGAs

Tunable Fine-grained Clock Phase-shifting for FPGAs

引用

international conference on field programmable logic and applications

作者： Bardia Babaei Dirk Koch Department of Computer Science The University of Manchester UK Institute of Computer Engineering Heidelberg University DE

High-resolution phase shifters have important practical applications in PET scanners, time-to-digital converters, and characterizing of the FPGA resources. This paper presents a fine-grained clock phase-shifting technique based on the FPGAs' clock managers' dynamic phase shifting capability that is commonly available on all recent FPGAs. Our method allows adjusting the phase shift resolution in the sub-picosecond range independent of the operating frequency. Experiments carried out on a Xilinx UltraScale+ FPGA show that phase-shifting resolution can be adjusted down to 88 f s in these devices. To verify the performance of this method, we have deployed it in a delay characterization circuit to measure the FPGA's resources delays. The experiments show that we can measure path delays below 1 ns which is impossible in conventional frequency sweep-based methods and we reach a much finer time resolution.

关键词： Performance evaluation Time-frequency analysis Voltage-controlled oscillators Phase shifters Frequency measurement Delays field programmable gate arrays

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Maia: Matrix Inversion Acceleration Near Memory

Maia: Matrix Inversion Acceleration Near Memory

引用

international conference on field programmable logic and applications

作者： Bahar Asgari Dheeraj Ramchandani Amaan Marfatia Hyesoon Kim University of Maryland College park Georgia Institute of Technology

Matrix inversion is an essential and challenging operation in several application domains, such as scientific computing, social networks, and recommendation systems. Since matrix inversion is a memory-bound task, it has the potential of being implemented near memory to efficiently use high memory bandwidth. However, data-dependency patterns in the common matrix-inversion algorithms limit memory bandwidth utilization. To minimize the negative impact of such dependencies on performance, we propose matrix inversion acceleration (Maia), a near-memory FPGA-based implementation of matrix inversion that converts the mathematical dependencies to gate-level dependencies thus reduces the critical-path latency. We implement and evaluate Maia on a high-end Xilinx Ultrascale+ xcu280 FPGA connected to a high-bandwidth memory (HBM2), targeting the data-center Alveo U280 boards. Maia performs matrix inversion 4 x faster than a baseline FPGA implementation without the proposed techniques for resolving dependencies.

关键词： Scientific computing Social networking (online) Memory management Bandwidth logic gates Matrix converters Task analysis

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DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators

DeLiBA: An Open-Source Hardware/Software Framework for the D...

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international conference on field programmable logic and applications

作者： Babar Khan Carsten Heinz Andreas Koch Embedded Systems and Applications Group TU Darmstadt Germany

With the trend towards ever larger “big data” applications, many of the gains achievable by using specialized compute accelerators become diminished due to the growing I/O overheads. While there have been a number of research efforts into computational storage and FPGA implementations of the NVMe interface, to our knowledge there have been only very limited efforts to move larger parts of the Linux block I/O stack into FPGA-based hardware accelerators. Our hardware/software framework DeLiBA aims to address this deficiency by allowing high-productivity development of software components of the I/O stack in user instead of kernel space, and leverages a proven FPGA SoC framework to quickly compose and deploy the actual FPGA-based I/O accelerators. While the current version of DeLiBA is focused on enabling more productive research instead of on raw performance, even in its current form it achieves 10% higher throughput and up to 2.3x the I/Os per second for a proof-of-concept Ceph accelerator realized using the system. These initial results show the large potential of performing further research in this acceleration domain.

关键词： Linux Throughput Market research Big Data applications Software Kernel field programmable gate arrays

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fpl Demo: 400G FPGA Packet Capture Based on Network Development Kit

FPL Demo: 400G FPGA Packet Capture Based on Network Developm...

引用

international conference on field programmable logic and applications

作者： Jakub Cabal Jiří Sikora Štepán Friedl Martin Špinler Jan Kořenek CESNET a. 1. e. Prague Czech Republic

CESNET, the Czech NREN (National Research and Education Network), has a long research history in the area of high-speed network monitoring using FPGA accelerated cards. Now, we are ready to present our open-source Network Development Kit for FPGAs 1 1 https://***/CESNET/ndk-app-minimal/ which is ready for 400 Gbps data transfers via Ethernet and PCI Express. The demo aims to show the possibilities of ndK, which allows users to quickly and easily develop new network applications for FPGA-based acceleration cards. Even high-speed DMA Module fully supported in ndK is available free of charge for academic purposes. It can thus significantly contribute to the spread of 400G technology in the academic community and also among other users. The accelerator card equipped with the Intel Agilex I-Series FPGA will transmit and receive back 400G Ethernet (400GBASE) traffic via external loopback. The received packets will be forwarded via very fast packet DMA transfers directly to the RAM of the host computer.

关键词： High-speed networks Education Random access memory Ethernet Data transfer History field programmable gate arrays

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RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices

RAD-Sim: Rapid Architecture Exploration for Novel Reconfigur...

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international conference on field programmable logic and applications

作者： Andrew Boutros Eriko Nurvitadhi Vaughn Betz University of Toronto and Vector Institute for AI Programmable Solutions Group Intel Corporation

With the continued growth in field-programmable gate array (FPGA) capacity and their incorporation into new environments such as datacenters, we have witnessed the introduction of a new class of reconfigurable acceleration devices (RADs) that go beyond conventional FPGA architectures. These devices combine a reconfigurable fabric with coarse-grained domain-specialized accelerator blocks all connected via a high-performance packet-switched network-on-chip (NoC) for efficient system-wide communication. However, we lack the tools necessary to efficiently explore the huge design space for RADs, study the complex interactions between their different components and evaluate various combinations of design choices. In this work, we develop RAD-Sim, a cycle-level architecture simulator that allows rapid application-driven exploration of the design space of novel RADs. To showcase the capabilities of RAD-Sim, we map and simulate a state-of-the-art deep learning (DL) inference overlay on a RAD instance incorporating an FPGA fabric and a complex of hard matrix-vector multiplication engines, communicating over a system-wide NoC. Through this example, we show how RAD-Sim can help architects quantify the effect of changing specific architecture parameters on end-to-end application performance.

关键词： Performance evaluation Deep learning Technological innovation Network-on-chip Fabrics Hardware field programmable gate arrays

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Reduction of Bitstream Size for Low-Cost iCE40 FPGAs

Reduction of Bitstream Size for Low-Cost iCE40 FPGAs

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international conference on field programmable logic and applications

作者： Clemens Fritzsch Jörn Hoffmann Martin Bogdan Neuromorphic Information Processing Leipzig University Leipzig Germany

Reducing the bitstream size is important to lower external storage requirements and to speed-up the reconfiguration of field-programmable gate arrays (FPGAs). The most common methods for bitstream size reduction are based on dedicated hardware elements or dynamic partial reconfiguration. All of these properties are usually missing in low-cost FPGAs such as the Lattice iCE40 device family. In this paper we propose a lightweight compaction approach for iCE40 FPGAs. We present five methods for bitstream compaction: two adapted and three new. The methods work directly on the bitstream by removing unnecessary data and redundant commands. They are applicable independent of the synthesis toolchain and require neither repetition of synthesis steps nor modifications of the target system. Although our focus is on iCE40 devices, we additionally discuss the conditions for applying our approach to other targets. All five methods were implemented in an open-source compaction tool. We evaluate our approach with an iCE40 HX8K FPGA by synthesizing and compacting various projects. As a result, we achieve a reduction in bitstream size and reconfiguration time by up to 79 %.

关键词： Measurement Lattices Hardware Entropy Compaction Resource management field programmable gate arrays

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EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs

EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Ch...

引用

international conference on field programmable logic and applications

作者： Yee Yang Tan Felix Staudigl Lukas Jünger Anna Drewes Rainer Leupers Jan Moritz Joseph Institute for Communication Technologies and Embedded Systems RWTH Aachen University Germany Institute for Information and Communication Technologies Otto-von-Guericke Universität Magdeburg Germany

Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling compared to slow simulations. However, realistic test stimuli are challenging to generate in hardware for diverse applications. In other words, both a fast and flexible design framework is required. The most promising solution is hybrid emulation, in which parts of the design are simulated in software, and the other parts are emulated in hardware. This paper proposes a novel hybrid emulation framework called EmuNoC. We introduce a clock-synchronization method and software-only packet generation that improves the emulation speed by 36.3 × to 79.3 × over state-of-the-art frameworks while retaining the flexibility of a pure-software interface for stimuli simulation. We also increased the area efficiency to model up to an NoC with 169 routers on a single FPGA, while previous frameworks only achieved 64 routers.

关键词： Emulation Network-on-chip Computer architecture Benchmark testing Software Hardware field programmable gate arrays

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