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检索条件"任意字段=33rd International Conference on Field-Programmable Logic and Applications, FPL 2023"

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Proceedings - 2023 33rd international conference on field-programmable logic and applications, fpl 2023

Proceedings - 2023 33rd International Conference on Field-Pr...

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33rd international conference on field-programmable logic and applications, fpl 2023

ISBN: (纸本)9798350341515

The proceedings contain 63 papers. The topics discussed include: compiler discovered dynamic scheduling of irregular code in high-level synthesis;challenges using FPGA clusters for distributed CNN training;HashCache: high-performance state tracking for resilient FPGA-based packet processing;Co-Visu: a video super-resolution accelerator exploiting codec information reuse;exploring highly quantized neural networks for intrusion detection in automotive CAN;Titan 2.0: enabling open-source CAD evaluation with a modern architecture capture;pipeline balancing for integrated mapping in high performance spatial programmable architecture;FPGA-accelerated causal discovery with conditional independence test prioritization;and fpl demo: a learning-based motion artefact detector for heterogeneous platforms.

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Exploring FPGA Acceleration for Distributed Serverless Computing 33

Exploring FPGA Acceleration for Distributed Serverless Compu...

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33rd international conference on field-programmable logic and applications (fpl)

作者： Yang, Ziyi Fahmy, Suhaib A. KAUST Thuwal Saudi Arabia

ISBN: (纸本)9798350341515

Serverless computing has become a popular cloud computing paradigm. However, its deployment abstraction entails significant performance overheads. We explore the potential for enabling serverless computing on FPGAs and present some early results that show the concurrency and scalability benefits on a stream processing workload. The FPGA enables flows of network data to flow directly into accelerators, which is beneficial for scenarios involving large packets and multiple request streams.

关键词： field programmable gate arrays (FPGA)

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Hardware-aware AutoML for Exploration of Custom FPGA Accelerators for RadioML 33

Hardware-aware AutoML for Exploration of Custom FPGA Acceler...

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33rd international conference on field-programmable logic and applications (fpl)

作者： Jentzsch, Felix Paderborn Univ Comp Engn Grp Paderborn Germany

ISBN: (纸本)9798350341515

This PhD project aims to tackle the laborious design process of FPGA-based deep neural network (DNN) inference solutions by combining automatic machine learning (AutoML) algorithms with a compiler for custom-tailored dataflow accelerator architectures. Manual experiments on a first use case from the RadioML domain suggests great potential for joint optimization of DNN and accelerator, but emphasize the need for empirical quality-of-result (QoR) estimation models, which are the current focus of the project. Future work will entail design space modeling and evaluation of state-of-the-art exploration techniques.

关键词： field programmable gate arrays (FPGA)

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SPADES: A Productive Design Flow for Versal programmable logic 33

SPADES: A Productive Design Flow for Versal Programmable Log...

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33rd international conference on field-programmable logic and applications (fpl)

作者： Tan Nguyen Blair, Zachary Neuendorffer, Stephen Wawrzynek, John Univ Calif Berkeley Berkeley CA 94720 USA AMD San Jose CA USA

ISBN: (纸本)9798350341515

With the increasing growth of complexity and heterogeneity of modern FPGA fabrics, the conventional "flat" design flow relying on the standard tools, from Synthesis, Implementation, to Bitstream Generation, has become more arduous than ever. This leads to an inordinate turn-around time which severely impacts the productivity of application developers in quest of design space exploration. We propose an open-source tool flow built around a customizable overlay of Spatially Distributed Socket Engines (SPADES) to address the FPGA productivity issue. SPADES organizes the computation and communication of an application in a parallel, distributed execution of socket engines. To tackle the compilation time issue, we exploit the hardened Network-on-Chip present in Versal, a novel commercial FPGA architecture from AMD, to alleviate the inter-socket routing task, as well as implement reusable socket netlist by utilizing regular programmable fabric regions. We use three data-parallel benchmarks to demonstrate that our tool flow achieves shorter compilation time than the standard, top-down AMD Vitis flow by 7x on average (from hours down to minutes) with comparable or better performance on the AMD Versal VCK5000 data center card.

关键词： Engines

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Accelerating the ATDCA Algorithm for Endmember Extraction from Hyperspectral Imagery with Intel oneAPI for FPGAs 33

Accelerating the ATDCA Algorithm for Endmember Extraction fr...

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33rd international conference on field-programmable logic and applications (fpl)

作者： Macias, Ruben Bernabe, Sergio Gonzalez, Carlos Univ Complutense Madrid E-28040 Madrid Spain

ISBN: (纸本)9798350341515

The decomposition of the observed pixel spectrum of hyperspectral data into its constituent spectral signatures (or endmembers) and a set of corresponding fractional abundances is known as hyperspectral unmixing. To carry out this analysis, it is required to use a computational technology with high-performance computing due to the high dimensionality of the data and the high complexity of the unmixing algorithms. field programmable Gate Arrays (FPGAs) are excellently suited to processing needs since they provide flexibility, low power consumption, and great performance. Faster alternative development methods are needed because the rate at which new algorithms for hyperspectral analysis are developed is substantially higher than the rate at which these algorithms are implemented on FPGAs. High-level synthesis (HLS) is a technology that assists with the transformation of a behavioral description of hardware into a register transfer level (RTL) model, thus reducing development times. In this work, the automatic target classification and detection algorithm (ATDCA) has been accelerated on FPGAs using Dataparalell C++ (DPC++) and Intel oneAPI. The analysis of the algorithm and the three accelerations carried out achieve a speedup above 13x.

关键词： Automatic target classification and detection algorithm (ATDCA) endmember extraction hyperspectral imagery Intel oneAPI field-programmable gate arrays (FPGAs)

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GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization 33

GNNBuilder: An Automated Framework for Generic Graph Neural ...

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33rd international conference on field-programmable logic and applications (fpl)

作者： Abi-Karam, Stefan Hao, Cong Georgia Inst Technol Atlanta GA 30332 USA Georgia Tech Res Inst Atlanta GA 30332 USA

ISBN: (纸本)9798350341515

There are plenty of graph neural network (GNN) accelerators being proposed. However, they highly rely on users' hardware expertise and are usually optimized for one specific GNN model, making them challenging for practical use. Therefore, in this work, we propose GNNBuilder, the first automated, generic, end-to-end GNN accelerator generation framework. It features four advantages: (1) GNNBuilder can automatically generate GNN accelerators for a wide range of GNN models arbitrarily defined by users;(2) GNNBuilder takes standard PyTorch programming interface, introducing zero overhead for algorithm developers;(3) GNNBuilder supports end-to-end code generation, simulation, accelerator optimization, and hardware deployment, realizing push-button GNN accelerator design;(4) GNNBuilder is equipped with accurate performance models for its generated accelerators, enabling fast and flexible design space exploration (DSE). In the experiments, we show that our accelerator performance model has errors within 36% for latency prediction and 18% for BRAM count prediction. Additionally, we show that our generated accelerators can outperform CPU by 6.33x and GPU by 6.87x. This framework is open-source, and the code is available at https://***/sharc- lab/gnn-builder.

关键词： field programmable Gate Arrays (FPGA) Graph Neural Network Graph Neural Network, High Level Synthesis Hardware Accelerator

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HyperGRAF: Hyperdimensional Graph-based Reasoning Acceleration on FPGA 33

HyperGRAF: Hyperdimensional Graph-based Reasoning Accelerati...

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33rd international conference on field-programmable logic and applications (fpl)

作者： Chen, Hanning Zakeri, Ali Wen, Fei Barkam, Hamza Errahmouni Imani, Mohsen Univ Calif Irvine Irvine CA 92697 USA Texas A&M Univ College Stn TX 77843 USA

ISBN: (纸本)9798350341515

The latest hardware accelerators proposed for graph applications primarily focus on graph neural networks (GNNs) and graph mining. High-level graph reasoning tasks, such as graph memorization and neighborhood reconstruction, have barely been addressed. Compared to low-level learning applications like node classification and clustering, high-level reasoning typically requires a more complex model to mimic human brain functionalities. Brain-inspired Hyper-Dimensional Computing (HDC) has recently introduced a promising lightweight and efficient machine learning solution, particularly for symbolic representation. General-purpose computing platforms (CPU/GPU) have been revealed to be inefficient for HDC applications. Therefore, it becomes essential to design a domain-specific accelerator targeting HDC-based graph reasoning algorithms. In this work, we propose the first domain-specific accelerator for HDC-based graph reasoning, HyperGRAF. We first develop a scheduler to balance the sparse matrix computation workloads, before parallelizing the hypervector calculations on two levels for the graph memorization task. Finally, we design a pipeline-style matrix multiplication accelerator for the neighborhood reconstruction task. We evaluate our design under a wide range of generated graphs with different sizes and sparsity. The results show that HyperGRAF achieves over 100x improvement in both speedup and energy efficiency of graph reasoning compared to NVIDIA Jetson Orin.

关键词： field programmable gate arrays (FPGA)

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A New, Reconfigurable Circuit Offering Functionality of AND and OR logic Gates for Use in Algorithms Implemented in Hardware 33

A New, Reconfigurable Circuit Offering Functionality of AND ...

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33rd IEEE international conference on Microelectronics, MIEL 2023

作者： Talaska, Tomasz Dlugosz, Rafal Nikolic, Tatjana Nikolic, Goran Stefanski, Tomasz Dlugosz, Michal Talaska, Michal Bydgoszcz University of Science and Technology Faculty of Telecommunication Computer Science and Electrical Engineering Bydgoszcz85-796 Poland Aptiv Services Poland Kraków30-399 Poland University of Niš Faculty of Electronic Engineering Niš18000 Serbia Gdanśk Univeristy of Technology Faculty of Electronics Telecommunications and Informatics Gdanśk80-233 Poland Poznan University of Technology Faculty of Control Robotics and Electrical Engineering Poznan60-965 Poland Complex of Electronics Schools Bydgoszcz85-092 Poland

ISBN: (纸本)9798350347760

The paper presents a programmable (using a 1-bit signal) digital gate that can operate in one of two OR or AND modes. A circuit of this type can also be implemented using conventional logic gates. However, in the case of the proposed circuit, compared to conventional solutions, the advantage is a much smaller number of transistors necessary for its implementation. Circuit is also much faster than its conventional counterpart. The logic gate was implemented in the 180nm CMOS technology and verified using Hspice simulations. There are many possible applications for this gate, mostly in artificial intelligence and pattern recognition algorithms implemented at the transistor level. © 2023 IEEE.

关键词： logic gates

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SPADES: A Productive Design Flow for Versal programmable logic

SPADES: A Productive Design Flow for Versal Programmable Log...

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international conference on field programmable logic and applications

作者： Tan Nguyen Zachary Blair Stephen Neuendorffer John Wawrzynek UC Berkeley AMD

With the increasing growth of complexity and heterogeneity of modern FPGA fabrics, the conventional “flat” design flow relying on the standard tools, from Synthesis, Implementation, to Bitstream Generation, has become more arduous than ever. This leads to an inordinate turn-around time which severely impacts the productivity of application developers in quest of design space exploration. We propose an open-source tool flow built around a customizable overlay of Spatially Distributed Socket Engines (SPADES) to address the FPGA productivity issue. SPADES organizes the computation and communication of an application in a parallel, distributed execution of socket engines. To tackle the compilation time issue, we exploit the hardened Network-on-Chip present in Versal, a novel commercial FPGA architecture from AMD, to alleviate the inter-socket routing task, as well as implement reusable socket netlist by utilizing regular programmable fabric regions. We use three data-parallel benchmarks to demonstrate that our tool flow achieves shorter compilation time than the standard, top-down AMD Vitis flow by 7x on average (from hours down to minutes) with comparable or better performance on the AMD Versal VCK5000 data center card.

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Feasibility Study for Future Implantable Neural-Silicon Interface Devices

Feasibility Study for Future Implantable Neural-Silicon Inte...

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33rd Annual international conference of the IEEE Engineering-in-Medicine-and-Biology-Society (EMBS)

作者： Al-armaghany, Allann Yu, Bo Mak, Terrence Tong, Kin-Fai Sun, Yihe UCL Dept Elect & Elect Engn London England

ISBN: (纸本)9781424441228

The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and trans-mission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. field programmable logic arrays (FPGAs) are used to evaluate various structures.

关键词： Antenna radiation patterns FPGA Hardware Hebbian eigenfilter Microstrip Microstrip antennas Patch antennas Real time systems Si Sorting artificial systems bioelectric phenomena brain brain-computer interfaces elemental semiconductors field programmable ga

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