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39th acm sigplan conference on programming language design and implementation (PLDI)

作者： Tran, Kim-Anh Jimborean, Alexandra Carlson, Trevor E. Koukos, Konstantinos Sjalander, Magnus Kaxiras, Stefanos Uppsala Univ Uppsala Sweden Natl Univ Singapore Singapore Singapore Norwegian Univ Sci & Technol NTNU Trondheim Norway

ISBN: (纸本)9781450356985

Increasing demands for energy eiciency constrain emerging hardware. these new hardware trends challenge the established assumptions in code generation and force us to rethink existing software optimization techniques. We propose a cross-layer redesign of the way compilers and the underlying microarchitecture are built and interact, to achieve both performance and high energy eiciency. In this paper, we address one of the main performance bottlenecksDlast-level cache misses-through a software-hardware co-design. Our approach is able to hide memory latency and attain increased memory and instruction level parallelism by orchestrating a non-speculative, execute-ahead paradigm in software (SWOOP). While out-of-order (OoO) architectures attempt to hide memory latency by dynamically reordering instructions, they do so through expensive, power-hungry, speculative mechanisms. We aim to shift this complexity into software, and we build upon compilation techniques inherited from VLIW, software pipelining, modulo scheduling, decoupled access-execution, and software prefetching. In contrast to previous approaches we do not rely on either software or hardware speculation that can be detrimental to eiciency. Our SWOOP compiler is enhanced with lightweight architectural support, thus being able to transform applications that include highly complex control-low and indirect memory accesses. the efectiveness of our software-hardware co-design is proven on the most limited but energy-eicient micro-architectures, non-speculative, in-order execution (InO) cores, which rely entirely on compile-time instruction scheduling. We show that (1) our approach achieves its goal in hiding the latency of the last-level cache misses and improves performance by 34% and energy eiciency by 23% over the baseline InO core, competitive with an oracle InO core with a perfect last-level cache;(2) can even exceed the performance of the oracle core, by exposing a higher degree of memory and instruction level

关键词： hardware-software co-design compilers memory level parallelism

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Babelsberg/JS A Browser-Based implementation of an Object Constraint language

Babelsberg/JS A Browser-Based Implementation of an Object Co...

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28th European conference on Object-Oriented programming (ECOOP)

作者： Felgentreff, Tim Borning, Alan Hirschfeld, Robert Lincke, Jens Ohshima, Yoshiki Freudenberg, Bert Krahn, Robert Univ Potsdam Hasso Plattner Inst Potsdam Germany Univ Washington Seattle WA 98195 USA Viewpoints Res Inst Los Angeles CA USA SAP Labs Commun Design Grp San Francisco CA USA

ISBN: (纸本)9783662442029;9783662442012

Constraints provide a useful technique for ensuring that desired properties hold in an application. As a result, they have been used in a wide range of applications, including graphical layout, simulation, scheduling, and problem-solving. We describe the design and implementation of an Object Constraint programming language, an object-oriented language that cleanly integrates constraints with the underlying language in a way that respects encapsulation and standard object-oriented programming techniques, and that runs in browser-based applications. Prior work on Object Constraint programming languages has relied on modifying the underlying Virtual Machine, but that is not an option for web-based applications, which have become increasingly prominent. In this paper, we present an approach to implementing Object Constraint programming without Virtual Machine support, along with an implementation as a JavaScript extension. We demonstrate the resulting language, Babelsberg/JS, on a number of applications and provide performance measurements. Programs without constraints in Babelsberg/JS run at the same speed as pure JavaScript versions, while programs that do have constraints can still be run efficiently. Our design and implementation also incorporate incremental re-solving to support interaction, as well as a cooperating solvers architecture that allows multiple solvers to work together to solve more difficult problems.

关键词： Constraints Object Constraint programming

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PolyMage: Automatic Optimization for Image Processing Pipelines 15

PolyMage: Automatic Optimization for Image Processing Pipeli...

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20th International conference on Architectural Support for programming languages and Operating Systems (ASPLOS)

作者： Mullapudi, Ravi Teja Vasista, Vinay Bondhugula, Uday Indian Inst Sci Dept Comp Sci & Automat Bangalore 560012 Karnataka India

ISBN: (纸本)9781450328357

this paper presents the design and implementation of PolyMage, a domain-specific language and compiler for image processing pipelines. An image processing pipeline can be viewed as a graph of interconnected stages which process images successively. Each stage typically performs one of point-wise, stencil, reduction or data-dependent operations on image pixels. Individual stages in a pipeline typically exhibit abundant data parallelism that can be exploited with relative ease. However, the stages also require high memory bandwidth preventing effective utilization of parallelism available on modern architectures. For applications that demand high performance, the traditional options are to use optimized libraries like OpenCV or to optimize manually. While using libraries precludes optimization across library routines, manual optimization accounting for both parallelism and locality is very tedious. the focus of our system, PolyMage, is on automatically generating high-performance implementations of image processing pipelines expressed in a high-level declarative language. Our optimization approach primarily relies on the transformation and code generation capabilities of the polyhedral compiler framework. To the best of our knowledge, this is the first model-driven compiler for image processing pipelines that performs complex fusion, tiling, and storage optimization automatically. Experimental results on a modern multicore system show that the performance achieved by our automatic approach is up to 1.81x better than that achieved through manual tuning in Halide, a state-of-the-art language and compiler for image processing pipelines. For a camera raw image processing pipeline, our performance is comparable to that of a hand-tuned implementation.

关键词： Domain-specific language image processing polyhedral optimization locality parallelism tiling multicores vectorization

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Surgical Precision JIT Compilers 14

Surgical Precision JIT Compilers

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35th acm sigplan conference on programming language design and implementation (PLDI)

作者： Rompf, Tiark Sujeeth, Arvind K. Brown, Kevin J. Lee, HyoukJoong Chafi, Hassan Olukotun, Kunle EPFL Zurich Switzerland Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781450327848

Just-in-time (JIT) compilation of running programs provides more optimization opportunities than offline compilation. Modern JIT compilers, such as those in virtual machines like Oracle's HotSpot for Java or Google's V8 for JavaScript, rely on dynamic profiling as their key mechanism to guide optimizations. While these JIT compilers offer good average performance, their behavior is a black box and the achieved performance is highly unpredictable. In this paper, we propose to turn JIT compilation into a precision tool by adding two essential and generic metaprogramming facilities: First, allow programs to invoke JIT compilation explicitly. this enables controlled specialization of arbitrary code at run-time, in the style of partial evaluation. It also enables the JIT compiler to report warnings and errors to the program when it is unable to compile a code path in the demanded way. Second, allow the JIT compiler to call back into the program to perform compile-time computation. this lets the program itself define the translation strategy for certain constructs on the fly and gives rise to a powerful JIT macro facility that enables "smart" libraries to supply domain-specific compiler optimizations or safety checks. We present Lancet, a JIT compiler framework for Java bytecode that enables such a tight, two-way integration with the running program. Lancet itself was derived from a high-level Java bytecode interpreter: staging the interpreter using LMS (Lightweight Modular Staging) produced a simple bytecode compiler. Adding abstract interpretation turned the simple compiler into an optimizing compiler. this fact provides compelling evidence for the scalability of the staged-interpreter approach to compiler construction. In the case of Lancet, JIT macros also provide a natural interface to existing LMS-based toolchains such as the Delite parallelism and DSL framework, which can now serve as accelerator macros for arbitrary JVM bytecode.

关键词： design languages Performance JIT Compilation Staging Program Generation

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Towards an implementation of differential dynamic logic in PVS 11

Towards an implementation of differential dynamic logic in P...

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11th acm sigplan International Workshop on the State Of the Art in Program Analysis, SOAP 2022, co-located with the 43rd acm sigplan International conference on programming language design and implementation, PLDI 2022

作者： Slagel, J. Tanner Muñoz, César Balachandran, Swee Moscato, Mariano Dutle, Aaron Masci, Paolo White, Lauren Nasa Langley Research Center United States National Institute of Aerospace United States

ISBN: (纸本)9781450392747

this paper describes an ongoing effort to embed and verify differential dynamic logic (dL) in the Prototype Verification System (PVS). dL is a logic for specifying and formally reasoning about hybrid systems, i.e., systems that employ both continuous and discrete dynamics. there are several benefits of this effort. First, the embedding of dL in PVS offers an independent formal verification of the semantics and inference rules of dL. Second, the embedding is fully operational within PVS, giving PVS practitioners the ability to use dL in the formal specification and verification of hybrid systems. third, the rich specification language, type system, and powerful interactive prover of PVS can be used on dL objects. In addition to the embedding and verification of dL, a custom extension for Visual Studio Code has been developed, so that a stylized dL syntax can be used to specify hybrid programs and their properties. © 2022 acm.

关键词： Hybrid systems

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Morello MicroPython: A Python Interpreter for CHERI 20

Morello MicroPython: A Python Interpreter for CHERI

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20th acm sigplan International conference on Managed programming languages and Runtimes (MPLR)

作者： Lowther, Duncan Jacob, Dejice Singer, Jeremy Univ Glasgow Glasgow Scotland

ISBN: (纸本)9798400703805

Arm Morello is a prototype system that supports CHERI hardware capabilities for improving runtime security. As Morello becomes more widely available, there is a growing effort to port open source code projects to this novel platform. Although high-level applications generally need minimal code refactoring for CHERI compatibility, low-level systems code bases require significant modification to comply with the stringent memory safety constraints that are dynamically enforced by Morello. In this paper, we describe our work on porting the MicroPython interpreter to Morello with the CheriBSD OS. Our key contribution is to present a set of generic lessons for adapting managed runtime execution environments to CHERI, including (1) a characterization of necessary source code changes, (2) an evaluation of runtime performance of the interpreter on Morello, and (3) a demonstration of pragmatic memory safety bug detection. Although MicroPython is a lightweight interpreter, mostly written in C, we believe that the changes we have implemented and the lessons we have learned are more widely applicable. To the best of our knowledge, this is the first published description of meaningful experience for scripting language runtime engineering with CHERI and Morello.

关键词： CHERI capabilities software implementation

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Generative software product line development using variability-aware design patterns

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COMPUTER languageS SYSTEMS & STRUCTURES 2017年 48卷 89-111页

作者： Seidl, Christoph Schuster, Sven Schaefer, Ina Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany

Software Product Lines (SPLs) are an approach to reuse in-the-large that models a set of closely related software systems in terms of commonalities and variabilities. design patterns are best practices for addressing recurring design problems in object-oriented source code. In the practice of implementing SPL, instances of certain design patterns are employed to handle variability, which makes these "variability-aware design patterns" a best practice for SPL design. However, currently there is no dedicated method for proactively developing SPLs using design patterns suitable for realizing variable functionality. In this paper, we present a method to perform generative SPL development with design patterns. We use role models to capture design patterns and their relation to a variability model. We further allow mapping of individual design pattern roles to (parts of) implementation elements to be generated (e.g., classes, methods) and check the conformance of the realization with the specification of the pattern. We provide definitions for the variability-aware versions of the design patterns Observer, Strategy, Template Method and Composite. Furthermore, we support generation of realization's in Java, C++ and UML class diagrams utilizing annotative, compositional and transformational variability realization mechanisms. Hence, we support proactive development of SPLs using design patterns to apply best practices for the realization of variability. We realize our concepts within the Eclipse IDE and demonstrate them within a case study. (C) 2016 Elsevier Ltd. All rights reserved.

关键词： SOFTWARE product line engineering COMPUTER software development SOFTWARE patterns REALIZATION (Linguistics) JAVA (Computer program language) C++ (Computer program language)

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Hera-JVM: A Runtime System for Heterogeneous Multi-Core Architectures 10

Hera-JVM: A Runtime System for Heterogeneous Multi-Core Arch...

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conference on Object Oriented programming Systems, languages and Applications/SPLASH 2010

作者： McIlroy, Ross Sventek, Joe Microsoft Res Cambridge Cambridge England Univ Glasgow Glasgow G12 8QQ Lanark Scotland

ISBN: (纸本)9781450302036

Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores support different instruction set architectures, and the processor as a whole does not provide coherence between the different cores' local memories. We present Hera-JVM, an implementation of the Java Virtual Machine which operates over the Cell processor, thereby making this platforms more readily accessible to mainstream developers. Hera-JVM supports the full Java language;threads from an unmodified Java application can be simultaneously executed on both the main PowerPC-based core and on the additional SPE accelerator cores. Migration of threads between these cores is transparent from the point of view of the application, requiring no modification to Java source code or bytecode. Hera-JVM supports the existing Java Memory Model, even though the underlying hardware does not provide cache coherence between the different core types. We examine Hera-JVM's performance under a series of real-world Java benchmarks from the SpecJVM, Java Grande and Dacapo benchmark suites. these benchmarks show a wide variation in relative performance on the different core types of the Cell processor, depending upon the nature of their workload. Execution of these benchmarks on Hera-JVM can achieve speedups of up to 2.25x by using one of the Cell processor's SPE accelerator cores, compared to execution on the main PowerPC-based core. When all six SPE cores are exploited, parallel workloads can achieve speedups of up to 13x compared to execution on the single PowerPC core.

关键词： design languages Performances

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Parameterized types for Java

Parameterized types for Java

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the 1997 24th acm sigplan-SIGACT Symposium on Principles of programming languages, POPL'97

作者： Myers, Andrew C. Bank, Joseph A. Liskov, Barbara Massachusetts Inst of Technology Cambridge MA United States

Java offers the real possibility that most programs can be written in a type-safe language. However, for Java to be broadly useful, it needs additional expressive power. this paper extends Java in one area where more power is needed: support for parametric polymorphism, which allows the definition and implementation of generic abstractions. We discuss both the rationale for our design decisions and the impact of the extension on other parts of Java, including arrays and the class library. We also describe optional extensions to the Java virtual machine to allow parameterized bytecodes, and how to verify them efficiently. We have extended the Jave bytecode interpreter to provide good performance for parameterized code in both execution speed and code size, without slowing down non-parameterized code.

关键词： Object oriented programming

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iTasks: Executable specifications of interactive work flow systems for the web

iTasks: Executable specifications of interactive work flow s...

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12th acm sigplan International conference on Functional programming

作者： Plasmeijer, Rinus Achten, Peter Koopman, Pieter Radboud Univ Nijmegen Inst Comp & Informat Sci Software Technol Dept NL-6525 ED Nijmegen Netherlands

ISBN: (纸本)9781595938152

In this paper we introduce the iTask system: a set of combinators to specify work flows in a pure functional language at a very high level of abstraction. Work flow systems are automated systems in which tasks are coordinated that have to be executed by humans and computers. the combinators that we propose support work flow patterns commonly found in commercial work flow systems. Compared with most of these commercial systems, the iTask system offers several advantages: tasks are statically typed, tasks can be higher order, the combinators are fully compositional, dynamic and recursive work flows can be specified, and last but not least, the specification is used to generate an executable web-based multi-user work flow application. With the iTask system, useful work flows can be defined which cannot be expressed in other systems: work can be interrupted and subsequently directed to other workers for further processing. the implementation is special as well. It is based on the Clean iData toolkit which makes it possible to create fully dynamic, interactive, thin client web applications. thanks to the generic programming techniques used in the iData toolkit, the programming effort is reduced significantly: state handling, form rendering, user interaction, and storage management is handled automatically. the iTask system allows a task to be regarded as a special kind of persistent redex being reduced by the application user via task completion. the combinators control the order in which these redexes are made available to the application user. the system rewrites the persistent task redexes in a similar way as functions are rewritten in lazy functional languages.

关键词： design languages clean iData iTask

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