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DeduDeep: An Extensible Framework for Combining Deep Learning and ASP-Based Models 16th

DeduDeep: An Extensible Framework for Combining Deep Learnin...

引用

16th international conference on logic programming and Non-Monotonic Reasoning (LPNMR)

作者： Bruno, Pierangela Calimeri, Francesco Marte, Cinzia Univ Calabria Dept Math & Comp Sci Arcavacata Di Rende Italy

ISBN: (纸本)9783031157073;9783031157066

In the last decades, Deep Learning (DL)-based approaches have been fruitfully employed in many tasks, such as providing valuable support to computer-aided diagnosis and medicine. However, DL-based approaches are known to suffer from some limitations;for instance, they lack of proper means for providing clear explanations and interpretations of the results, or explicitly including available knowledge to drive decisions. In this work, we present DeduDeep, the prototypical implementation of a framework explicitly conceived with the aim of tackling such limitations by making use of deductive declarative formalisms. In particular, the framework aims at enabling the declarative encoding of explicit knowledge, and, by relying on the use of Answer Set programming (ASP), taking advantage of it for driving decisions taken by neural networks and refining the output. the framework has been tested using different artificial neural networks tailored to semantic segmentation tasks over Laryngeal Endoscopic Images and Freiburg Sitting People Images.

关键词： Answer Set programming Knowledge Representation and Reasoning Non-monotonic reasoning Deep Learning Semantic Segmentation Inductive-deductive coupling

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the Energy Cost of the Visitor Pattern 39

The Energy Cost of the Visitor Pattern

引用

39th IEEE international conference on Software Maintenance and Evolution (ICSME)

作者： Bree, Deaglan Connolly Cinneide, Mel O. Univ Coll Dublin Sch Comp Sci Dublin Ireland

ISBN: (数字)9781665479561

ISBN: (纸本)9781665479561

Design patterns are applied frequently during software evolution in order to make the software more flexible and amenable to extension. One little-studied aspect of design patterns is their propensity to increase run time energy consumption due to the indirection and additional structure they introduce. In this paper we study the impact of the Visitor pattern on energy efficiency. the Visitor pattern separates an algorithm from the objects it acts upon and improves maintainability by placing each algorithm within a single visitor class, at the cost of increased indirection due to the double dispatch required when the algorithm is invoked. We experimentally investigate the energy impact of varying the implementation of this pattern, and of removing the pattern entirely from the software. In our results we observe energy consumption reductions of greater than 7% in the textbook example when the pattern is implemented using reflective casting, and reductions of over 10% when experimenting with an open source project, JavaParser. the complete removal of the pattern yields more complex results, with little impact in the textbook example but reductions of over 7% in the JavaParser study. Our results highlight the energy savings that may be achieved when the Visitor pattern is removed, and show that energy savings may also be achieved by varying the implementation of the pattern.

关键词： Empirical Design Patterns Visitor Pattern Green Technology Energy Efficiency Refactoring Software Transformation Software Design Object-Oriented programming

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Flash: A Framework for programming Distributed Graph Processing Algorithms

Flash: A Framework for Programming Distributed Graph Process...

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international conference on Data Engineering

作者： Xue Li Ke Meng Lu Qin Longbin Lai Wenyuan Yu Zhengping Qian Xuemin Lin Jingren Zhou Alibaba Group Centre for Artificial Intelligence University of Technology Sydney Australia Antai College of Economics & Management Shanghai Jiao Tong University

As a result of decades of studies, a broad spectrum of graph algorithms have been developed for graph analytics, including clustering, centrality, traversal, matching, mining, etc. However, the majority of recent graph processing frameworks only focus on a handful of fix-point graph algorithms such as breadth-first search, PageRank, shortest path, etc. It leaves the distributed computation of a large variety of graph algorithms suffering from low efficiency, limited expressiveness, or high implementation complexity with existing *** this paper, we propose Flash, a framework for programming distributed graph processing algorithms, which achieves good expressiveness, productivity and efficiency at the same time. thanks to its high-level interface, Flash allows users to implement complex distributed graph algorithms with high performance with only a few lines of code. We have implemented 72 graph algorithms for 49 different problems in Flash. In further evaluations, we found that Flash beats other state-of-the-art graph processing frameworks with the speedups of up to 2 orders of magnitudes while takes up to 92% less lines of code.

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Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets 39

Chopin: Composing Cost-Effective Custom Chips with Algorithm...

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39th IEEE international conference on Computer Design ICCD)

作者： Ehrett, Pete Austin, Todd Bertacco, Valeria Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781665432191

As computational demands rise, the need for specialized hardware has grown acute. However, the immense cost of fully-custom chips has forced many developers to rely on suboptimal solutions like FPGAs, especially for low- to mid-volume applications, in which multi-million-dollar non-recurring engineering (NRE) costs cannot be amortized effectively. We propose to address this problem by composing custom chips out of small, algorithmic chiplets, reusable across diverse designs, such that high NRE costs may be amortized across many different designs. this work models the economics of this paradigm and identifies a cost-optimal granularity for algorithmic chiplets, then demonstrates how those guidelines may be applied to design high-performance, algorithmically-composable hardware components - which may be reused, without modification, across many different processing pipelines. For an example phased-array radar accelerator, our chiplet-centric paradigm improves perf-per-$ by 9.3x over an FPGA, and similar to 4x over a conventional ASIC.

关键词： Industries Costs Biological system modeling Pipelines Hardware Silicon logic design

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ASP-Driven Emergency Planning for Norm Violations in Reinforcement Learning 39

ASP-Driven Emergency Planning for Norm Violations in Reinfor...

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39th Annual AAAI conference on Artificial Intelligence, AAAI 2025

作者： Adam, Sebastian Eiter, thomas Institute of Logic and Computation Vienna University of Technology Favoritenstraße 9-11 Vienna A-1040 Austria

ISBN: (纸本)157735897X

Reinforcement learning (RL) is a widely used approach for training an agent to maximize rewards in a given environment. Action policies learned with this technique see a broad range of applications in practical areas like games, healthcare, robotics, or autonomous driving. However, enforcing ethical behavior or norms based on deontic constraints that the agent should adhere to during policy execution remains a complex challenge. Especially constraints that emerge after the training can necessitate to redo policy learning, which can be costly and, more critically, time consuming. To mitigate this problem, we present a framework for policy fixing in case of a norm violation, which allows the agent to stay operational. Based on answer set programming (ASP), emergency plans are generated that exclude or minimize cost of norm violations by future actions in a horizon of interest. By combining and developing optimization techniques, efficient policy fixing under real-time constraints can be achieved. Copyright © 2025, Association for the Advancement of Artificial Intelligence (***). All rights reserved.

关键词： Reinforcement learning

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EFM: Elastic Flash Management to Enhance Performance of Hybrid Flash Memory 39

EFM: Elastic Flash Management to Enhance Performance of Hybr...

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39th IEEE international conference on Computer Design ICCD)

作者： Li, Bingzhe Yuan, Bo Du, David Oklahoma State Univ Stillwater OK 74078 USA Rutgers State Univ Piscataway NJ USA Univ Minnesota Twin Cities Minneapolis MN USA

ISBN: (纸本)9781665432191

NAND-based flash memory has become a prevalent storage media due to its low access latency and high performance. By setting up different incremental step pulse programming (ISPP) values and threshold voltages, the tradeoffs between lifetime and access latency in NAND-based flash memory can be exploited. the existing studies that exploit the tradeoffs by using heuristic algorithms do not consider the dynamically changed access latency due to wearing-out, resulting in low access performance. In this paper, we proposed a new Elastic Flash Management scheme, called EFM, to manage data in hybrid flash memory, which consists of multiple physical regions with different read/write latencies according to their ISPP values and threshold voltages. EFM includes a Long-Term Classifier (LT-Classifier) and a Short-Term Classifier (ST-Classifier) to accurately track dynamically changed workloads by considering current quantitative differences of read/write latencies and workload access patterns. Moreover, a reduced effective wearing management is proposed to prolong the lifetime of flash memory by scheduling write-intensive workloads to the region with a reduced threshold voltage and the lowest write cost. Experimental results indicate that EFM reduces the average read/write latencies by about 54% - 296% and obtain 17.7% lifetime improvement on average compared to the existing studies.

关键词： Costs Processor scheduling Heuristic algorithms conferences programming Media threshold voltage

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Column-Oriented Datalog on the GPU 39

Column-Oriented Datalog on the GPU

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39th Annual AAAI conference on Artificial Intelligence, AAAI 2025

作者： Sun, Yihao Kumar, Sidharth Gilray, thomas Micinski, Kristopher Syracuse University United States University of Illinois Chicago United States Washington State University United States

ISBN: (纸本)157735897X

Datalog is a logic programming language widely used in knowledge representation and reasoning (KRR), program analysis, and social media mining due to its expressiveness and high performance. Traditionally, Datalog engines use either row-oriented or column-oriented storage. Engines like VLog and Nemo favor column-oriented storage for efficiency on limited-resource machines, while row-oriented engines like Soufflé use advanced data structures with locking to perform better on multi-core CPUs. the advent of modern datacenter GPUs, such as the NVIDIA H100 with its ability to run over 16k threads simultaneously and high memory bandwidth, has reopened the debate on which storage layout is more effective. this paper presents the first column-oriented Datalog engines tailored to the strengths of modern GPUs. We present FVLOG, a CUDA-based Datalog runtime library with a column-oriented GPU datastructure that supports all necessary relational algebra operations. Our results demonstrate over 200× performance gains over SOTA CPU-based column-oriented Datalog engines and a 2.5× speedup over GPU Datalog engines in various workloads, including KRR. Copyright © 2025, Association for the Advancement of Artificial Intelligence (***). All rights reserved.

关键词： Constraint programming

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DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications 39

DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurabl...

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39th IEEE international conference on Computer Design ICCD)

作者： Tan, Cheng Geng, Tong Xie, Chenhao Agostini, Nicolas Bohm Li, Jiajia Li, Ang Barker, Kevin Tumeo, Antonino Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781665432191

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across kernels. However, streaming applications often are data-dependent, leading to variable kernel execution times depending on the input data and impacting the throughput of the entire pipeline if resources are statically allocated. therefore, in this paper, we discuss the design of DynPaC a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We discuss the required software and hardware components to manage partial dynamic reconfiguration. We demonstrate that by supporting partial dynamic reconfiguration, we can obtain an average speedup of 1.44 x for a representative set of applications w.r.t. static partitioning, with a limited area overhead (6.4% of the entire chip).

关键词： Reconfigurable devices conferences Pipelines logic gates throughput Software Arrays

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Is there a Transcript?: Mapping Access in the Multimodal Designs of Popular Podcasts 21

Is There a Transcript?: Mapping Access in the Multimodal Des...

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39th ACM international conference on the Design of Communication: Building Coalitions. Worldwide, SIGDOC 2021

作者： Chelsey, Amelia Embry-Riddle Aeronautical University United States

ISBN: (纸本)9781450386289

Podcasting has grown into an established mode of cultural production, knowledge making, and community building. though podcasts are commonly designed within multimodal content systems, transcript availability for many podcast series remains uneven. I survey the webpages of 94 English-language podcasts (two each sampled from 47 podcast production networks) in order to measure the availability and findability of official transcripts. With this research, I begin to both investigate the limits of podcasting's practical attention to access and question some of the values, priorities, and assumptions that underly the conventions of podcasting. Transcript availability matters for purposes of inclusion and for the empowerment of audiences who hope to engage with podcasting conversations for scholarship, activism, or coalition-building. this small study forms a foundation from which we can continue building the infrastructure needed to make transcripts more expected and more widely available. © 2021 ACM.

关键词： Computer programming

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HighGuard: Cross-Chain Business logic Monitoring of Smart Contracts

HighGuard: Cross-Chain Business Logic Monitoring of Smart Co...

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IEEE international conference on Automated Software Engineering (ASE)

作者： Mojtaba Eshghie Cyrille Artho Hans Stammler Wolfgang Ahrendt thomas T. Hildebrandt Gerardo Schneider KTH Royal Institute of Technology Stockholm Sweden Chalmers University of Technology Gothenburg Sweden University of Copenhagen Copenhagen Denmark University of Gothenburg Gothenburg Sweden

ISBN: (数字)9798400712487

ISBN: (纸本)9798331508241

logical flaws in smart contracts are often exploited, leading to significant financial losses. Our tool, HighGuard, detects transactions that violate business logic specifications of smart contracts. HighGuard employs dynamic condition response (DCR) graph models as formal specifications to verify contract execution against these models. It is capable of operating in a cross-chain environment for detecting business logic flaws across different blockchain platforms. We demonstrate HighGuard’s effectiveness in identifying deviations from specified behaviors in smart contracts without requiring code instrumentation or incurring additional gas costs. By using precise specifications in the monitor, HighGuard achieves detection without false positives. Our evaluation, involving 54 exploits, confirms HighGuard’s effectiveness in detecting business logic *** open-source implementation of HighGuard and a screencast of its usage are available at: https://***/mojtaba-eshghie/HighGuard https://***/watch?v=sZYVV-slDaYCCS CONCEPTS• Software and its engineering → Dynamic analysis; Software verification; Model checking; Functionality; Formal software verification; Software testing and debugging;• Security and privacy → Formal security models.

关键词： Software testing Codes Instruments Smart contracts Software logic Security Monitoring Business Software engineering

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